公开(公告)号：US20080046665A1

公开(公告)日：2008-02-21

申请号：US11745175

申请日：2007-05-07

申请人： Kyoung-park Kim

发明人： Kyoung-park Kim

IPC分类号： G06F12/00

CPC分类号： G11C7/1075 ,  G06F9/541 ,  G06F9/544 ,  G06F13/1663 ,  G06F13/1694 ,  G06F2209/543

摘要： A multiport memory device includes a first dedicated memory region, a second dedicated memory region, and a shared memory region. The first dedicated memory region can be accessed by a first, processor. The second dedicated memory region can be accessed fay a second processor. The shared memory region can be accessed by both the first processor and the second processor. The shared memory region and comprises an SRAM.

摘要翻译： 多端口存储器件包括第一专用存储器区域，第二专用存储器区域和共享存储器区域。 第一专用存储器区域可以由第一处理器访问。 第二专用存储器区域可以访问第二处理器。 第一处理器和第二处理器都可以访问共享存储器区域。 共享存储器区域并且包括SRAM。

公开(公告)号：US20060273827A1

公开(公告)日：2006-12-07

申请号：US11365691

申请日：2006-03-02

申请人： Kyoung-Park Kim

发明人： Kyoung-Park Kim

IPC分类号： G01R29/00

CPC分类号： H03L7/0814 ,  H03L7/0805 ,  H03L7/091 ,  H04L7/0008 ,  H04L7/0012 ,  H04L7/0337

摘要： An apparatus may include a first phase control circuit and/or a second phase control circuit. The first phase control circuit may compare the phase of the first clock signal with the phase of the second clock signal, and may control the phase of the first clock signal based on the result of the comparison. The second phase control circuit may control the phase of the second clock signal based on the result of the comparison output from the first phase control circuit. The first phase control circuit may control the phase of the first clock signal and/or the second phase control circuit may control the phase of the second clock signal such that they are synchronized with each other.

公开(公告)号：US20050256986A1

公开(公告)日：2005-11-17

申请号：US11124271

申请日：2005-05-09

申请人： Kyoung-Park Kim ,  Sung-Ho Ryu ,  Min-Soo Lim

发明人： Kyoung-Park Kim ,  Sung-Ho Ryu ,  Min-Soo Lim

IPC分类号： G06F13/38 ,  G06F1/32 ,  G06F13/00

CPC分类号： G06F1/3203

摘要： A slave device may be configured to receive at least one bus interface clock and bus interface signals from a bus coupled to the at least one bus interface unit. The slave device may also be configured to operate independently of at least one main function clock

摘要翻译： 从设备可以被配置为从耦合到至少一个总线接口单元的总线接收至少一个总线接口时钟和总线接口信号。 从设备还可以被配置为独立于至少一个主功能时钟来操作

公开(公告)号：US07586348B2

公开(公告)日：2009-09-08

申请号：US11365691

申请日：2006-03-02

申请人： Kyoung-Park Kim

发明人： Kyoung-Park Kim

IPC分类号： H03L7/00

CPC分类号： H03L7/0814 ,  H03L7/0805 ,  H03L7/091 ,  H04L7/0008 ,  H04L7/0012 ,  H04L7/0337

摘要： An apparatus may include a first phase control circuit and/or a second phase control circuit. The first phase control circuit may compare the phase of the first clock signal with the phase of the second clock signal, and may control the phase of the first clock signal based on the result of the comparison. The second phase control circuit may control the phase of the second clock signal based on the result of the comparison output from the first phase control circuit. The first phase control circuit may control the phase of the first clock signal and/or the second phase control circuit may control the phase of the second clock signal such that they are synchronized with each other.

摘要翻译： 装置可以包括第一相位控制电路和/或第二相位控制电路。 第一相位控制电路可以将第一时钟信号的相位与第二时钟信号的相位进行比较，并且可以基于比较的结果来控制第一时钟信号的相位。 第二相位控制电路可以基于来自第一相位控制电路的比较输出的结果来控制第二时钟信号的相位。 第一相位控制电路可以控制第一时钟信号的相位和/或第二相位控制电路可以控制第二时钟信号的相位，使得它们彼此同步。

公开(公告)号：US07154322B2

公开(公告)日：2006-12-26

申请号：US11039609

申请日：2005-01-20

申请人： Kyoung-Park Kim

发明人： Kyoung-Park Kim

IPC分类号： H03H11/26

CPC分类号： H03L7/0814 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222

摘要： A delay signal generator circuit is provided. A delay circuit including a plurality of series-connected inverters for sequentially delaying a first clock signal and for generating a plurality of delay signals and a multiplexer for selecting one of the delay signals. A delay control circuit samples the selected delay signal in response to a transition of a second clock signal. The second clock signal has twice the frequency of the first clock signal, and the delay control circuit controls the delay circuit based upon the sampled value(s) so that the selected delay signal output from the delay circuit has a delay time of ¼ clock cycle relative to the first clock signal.

摘要翻译： 提供延迟信号发生器电路。 一种延迟电路，包括多个串联连接的反相器，用于顺序地延迟第一时钟信号并产生多个延迟信号，以及多路复用器用于选择一个延迟信号。 响应于第二时钟信号的转变，延迟控制电路对所选择的延迟信号进行采样。 第二时钟信号具有第一时钟信号的两倍频率，并且延迟控制电路基于采样值控制延迟电路，使得从延迟电路输出的所选择的延迟信号具有1/4时钟周期的延迟时间 相对于第一时钟信号。

公开(公告)号：US07346723B2

公开(公告)日：2008-03-18

申请号：US11124271

申请日：2005-05-09

申请人： Kyoung-Park Kim ,  Sung-Ho Ryu ,  Min-Soo Lim

发明人： Kyoung-Park Kim ,  Sung-Ho Ryu ,  Min-Soo Lim

IPC分类号： G06F13/14

CPC分类号： G06F1/3203

摘要： A slave device may be configured to receive at least one bus interface clock and bus interface signals from a bus coupled to the at least one bus interface unit. The slave device may also be configured to operate independently of at least one main function clock.

摘要翻译： 从设备可以被配置为从耦合到至少一个总线接口单元的总线接收至少一个总线接口时钟和总线接口信号。 从设备还可以被配置为独立于至少一个主功能时钟来操作。

公开(公告)号：US20050156647A1

公开(公告)日：2005-07-21

申请号：US11039609

申请日：2005-01-20

申请人： Kyoung-Park Kim

发明人： Kyoung-Park Kim

IPC分类号： G06F12/00 ,  G11C7/22 ,  G11C11/40 ,  G11C11/409 ,  H03K5/13 ,  H03K5/153 ,  H03L7/06 ,  H03L7/081

CPC分类号： H03L7/0814 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222

摘要： A delay signal generator circuit is provided. A delay circuit including a plurality of series-connected inverters for sequentially delaying a first clock signal and for generating a plurality of delay signals and a multiplexer for selecting one of the delay signals. A delay control circuit samples the selected delay signal in response to a transition of a second clock signal. The second clock signal has twice the frequency of the first clock signal, and the delay control circuit controls the delay circuit based upon the sampled value(s) so that the selected delay signal output from the delay circuit has a delay time of ¼ clock cycle relative to the first clock signal.

摘要翻译： 提供延迟信号发生器电路。 一种延迟电路，包括多个串联连接的反相器，用于顺序地延迟第一时钟信号并产生多个延迟信号，以及多路复用器用于选择一个延迟信号。 响应于第二时钟信号的转变，延迟控制电路对所选择的延迟信号进行采样。 第二时钟信号具有第一时钟信号的两倍频率，并且延迟控制电路基于采样值控制延迟电路，使得从延迟电路输出的所选择的延迟信号具有1/4时钟周期的延迟时间 相对于第一时钟信号。

公开(公告)号：US07379367B2

公开(公告)日：2008-05-27

申请号：US10834757

申请日：2004-04-29

申请人： Kyoung-Park Kim

发明人： Kyoung-Park Kim

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/40611 ,  G11C11/406 ,  G11C11/40622 ,  G11C11/4087

摘要： A memory controller and a semiconductor device comprising the same are provided. The semiconductor device comprises a memory block comprising a plurality of memory banks and a memory controller. The memory controller outputs an auto refresh command and memory bank information indicating a memory bank that is to be auto refreshed in an auto refresh mode. Thus, only the selected memory bank performs an auto refresh operation in the auto refresh mode while reducing current consumption in the semiconductor device.

摘要翻译： 提供了一种存储器控制器和包括该存储器控制器的半导体器件。 该半导体器件包括一个包括多个存储体和存储器控制器的存储器块。 存储器控制器输出自动刷新命令和指示将在自动刷新模式下自动刷新的存储体的存储体信息。 因此，只有选择的存储体在自动刷新模式下执行自动刷新操作，同时减少半导体器件中的电流消耗。

公开(公告)号：US20050024969A1

公开(公告)日：2005-02-03

申请号：US10834757

申请日：2004-04-29

申请人： Kyoung-Park Kim

发明人： Kyoung-Park Kim

IPC分类号： G11C11/40 ,  G11C11/406 ,  G11C11/408 ,  G11C7/00

CPC分类号： G11C11/40611 ,  G11C11/406 ,  G11C11/40622 ,  G11C11/4087

摘要： A memory controller and a semiconductor device comprising the same are provided. The semiconductor device comprises a memory block comprising a plurality of memory banks and a memory controller. The memory controller outputs an auto refresh command and memory bank information indicating a memory bank that is to be auto refreshed in an auto refresh mode. Thus, only the selected memory bank performs an auto refresh operation in the auto refresh mode while reducing current consumption in the semiconductor device.

摘要翻译： 提供了一种存储器控制器和包括该存储器控制器的半导体器件。 该半导体器件包括一个包括多个存储体和存储器控制器的存储器块。 存储器控制器输出自动刷新命令和指示将在自动刷新模式下自动刷新的存储体的存储体信息。 因此，只有选择的存储体在自动刷新模式下执行自动刷新操作，同时减少半导体器件中的电流消耗。