公开(公告)号：US09218243B2

公开(公告)日：2015-12-22

申请号：US14123510

申请日：2012-05-14

申请人： Ian P. Shaeffer

发明人： Ian P. Shaeffer

IPC分类号： G06F11/10 ,  G11C7/10 ,  G11C5/04 ,  G11C29/04

CPC分类号： G06F11/108 ,  G06F11/1008 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1068 ,  G11C5/04 ,  G11C7/10 ,  G11C2029/0411

摘要： A memory system supporting error detection and correction (EDC) coverage. The system includes a memory controller and a memory buffer. The memory buffer includes an interface to a first group of memory devices and an interface to a second group of memory devices. The memory buffer accesses data from the first group of memory devices and accesses first error information corresponding to the data from the second group of devices. The memory buffer also accesses additional data from the second group of memory devices and accesses second error information corresponding to the additional data from a device in the first group of memory devices. EDC coverage may also be configured by the memory controller so that some data accesses have EDC coverage and other data accesses do not have EDC coverage.

摘要翻译： 支持错误检测和纠正（EDC）覆盖的存储器系统。 该系统包括存储器控制器和存储器缓冲器。 存储器缓冲器包括到第一组存储器件的接口和到第二组存储器件的接口。 存储器缓冲器访问来自第一组存储器件的数据，并访问与来自第二组器件的数据相对应的第一错误信息。 存储器缓冲器还访问来自第二组存储器设备的附加数据，并从第一组存储器件中的设备访问与附加数据相对应的第二错误信息。 EDC覆盖也可以由存储器控制器配置，使得一些数据访问具有EDC覆盖，而其他数据访问不具有EDC覆盖。

公开(公告)号：US08749042B2

公开(公告)日：2014-06-10

申请号：US13166996

申请日：2011-06-23

申请人： Frederick A. Ware ,  Ely K. Tsern ,  Ian P. Shaeffer

发明人： Frederick A. Ware ,  Ely K. Tsern ,  Ian P. Shaeffer

IPC分类号： H01L23/02 ,  H01L23/04 ,  H01L23/52

CPC分类号： H01L21/768 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/00

摘要： Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first device and the second device are subsequently stacked such that the first surface of the second device is located adjacent the second surface of the first device such that the first electrical contact of the second device is aligned with the third electrical contact of the first device. The first electrical contact of the second device is electrically connected to the third electrical contact of the first device.

摘要翻译： 包括第一设备和第二设备的多个设备具有操作电路和相对的第一和第二表面。 第一和第二电触点形成在第一表面处，而在与第一电触点相对的第二表面处形成第三电接触。 第一电触头电连接到操作电路，并且第二电触头电连接到第三电触头。 随后堆叠第一装置和第二装置，使得第二装置的第一表面位于第一装置的第二表面附近，使得第二装置的第一电触点与第一装置的第三电触点对准 。 第二器件的第一电接触电连接到第一器件的第三电接触件。

公开(公告)号：US20130201770A1

公开(公告)日：2013-08-08

申请号：US13640084

申请日：2012-06-08

申请人： James Edward Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

发明人： James Edward Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC分类号： G11C7/06

CPC分类号： G11C7/1039 ,  G11C5/025 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

摘要： Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

摘要翻译： 存储器组件内的行激活操作相对于子行执行，而不是完整的存储行，以减少功耗。 此外，代替激活响应于行命令的子代码，延迟激活操作被延迟，直到接收到指定要执行的列操作的列命令和被激活的子代。

公开(公告)号：US08380943B2

公开(公告)日：2013-02-19

申请号：US12808662

申请日：2009-01-07

申请人： Ian P. Shaeffer

发明人： Ian P. Shaeffer

IPC分类号： G06F12/00

CPC分类号： G06F13/1678 ,  G06F13/1694

摘要： A memory module having a plurality of memory devices and a memory buffer that translates between a variable width primary data port and a plurality of fixed width secondary data ports, each of which is coupled to one of the memory devices. The translation is effected by distributing the width of the primary data port to all or to a subset of the secondary data ports. In another aspect, the invention comprises a memory buffer that supports adjustable data width in a variety of ways.

摘要翻译： 具有多个存储器件的存储器模块和在可变宽度主数据端口和多个固定宽度辅助数据端口之间转换的存储器缓冲器，每个存储器模块耦合到存储器件之一。 翻译是通过将主数据端口的宽度分配给所有或次要数据端口的子集来实现的。 在另一方面，本发明包括以各种方式支持可调整数据宽度的存储器缓冲器。

公开(公告)号：US20110267101A1

公开(公告)日：2011-11-03

申请号：US13180550

申请日：2011-07-12

申请人： Kyung Suk Oh ,  Ian P. Shaeffer

发明人： Kyung Suk Oh ,  Ian P. Shaeffer

IPC分类号： H03K19/003

CPC分类号： H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

摘要： A control component outputs to an integrated circuit device an indication to apply one of a plurality of controllable termination impedance configurations at a data input of the integrated circuit device. The indication causes the integrated circuit device to apply a first of the controllable termination impedance configurations at the data input during a first internal state of the integrated circuit device corresponding to the reception of write data on the data input, and causes the integrated circuit device to apply a second of the controllable termination impedance configurations at the data input during a second internal state of the integrated circuit device that follows the first internal state.

摘要翻译： 控制部件向集成电路器件输出在集成电路器件的数据输入端施加多个可控终端阻抗配置中的一个的指示。 所述指示使得所述集成电路装置在所述集成电路装置的第一内部状态期间在所述数据输入处施加第一可控终端阻抗配置，所述第一内部状态对应于所述数据输入上的写数据的接收，并且使所述集成电路装置 在第一内部状态下的集成电路器件的第二内部状态期间，在数据输入端施加第二个可控终端阻抗配置。

公开(公告)号：US07989265B2

公开(公告)日：2011-08-02

申请号：US12361513

申请日：2009-01-28

申请人： Frederick A. Ware ,  Ely K. Tsern ,  Ian P. Shaeffer

发明人： Frederick A. Ware ,  Ely K. Tsern ,  Ian P. Shaeffer

IPC分类号： H01L21/00

CPC分类号： H01L21/768 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/00

摘要： Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first device and the second device are subsequently stacked such that the first surface of the second device is located adjacent the second surface of the first device such that the first electrical contact of the second device is aligned with the third electrical contact of the first device. The first electrical contact of the second device is electrically connected to the third electrical contact of the first device.

摘要翻译： 包括第一设备和第二设备的多个设备具有操作电路和相对的第一和第二表面。 第一和第二电触点形成在第一表面处，而在与第一电触头相对的第二表面处形成第三电接触。 第一电触头电连接到操作电路，并且第二电触头电连接到第三电触头。 随后堆叠第一装置和第二装置，使得第二装置的第一表面位于第一装置的第二表面附近，使得第二装置的第一电触点与第一装置的第三电触点对准 。 第二器件的第一电接触电连接到第一器件的第三电接触件。

公开(公告)号：US07924048B2

公开(公告)日：2011-04-12

申请号：US12861771

申请日：2010-08-23

申请人： Kyung Suk Oh ,  Ian P. Shaeffer

发明人： Kyung Suk Oh ,  Ian P. Shaeffer

IPC分类号： H03K17/16

CPC分类号： H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

摘要： A memory controller that controls termination in a memory device. The memory controller includes a data interface, command/address interface and termination control output. The data interface outputs write data onto a data line coupled to a data input of the memory device, and the command/address interfaces outputs, onto a command/address path coupled to the memory device, information that indicates whether the write data is to be received within the memory device. The termination control output asserts a first termination control signal on a termination control signal line coupled to the memory device to cause the memory device to either (i) couple a first termination impedance to the data line while the write data is present at the data input of the memory device if the information indicates that the write data is to be received within the memory device, or (ii) couple a second termination impedance to the data line while the write data is present at the data input of the memory device if the information indicates that the write data is not to be received within the memory device.

摘要翻译： 一个控制存储设备终端的存储控制器。 存储器控制器包括数据接口，命令/地址接口和终端控制输出。 数据接口将写入数据输出到与存储器件的数据输入端相连的数据线上，命令/地址接口输出到与存储器件相连的命令/地址通道上，指示写数据是否为 在存储器件内接收。 终端控制输出在耦合到存储器件的终端控制信号线上断言第一终止控制信号，以使得存储器件（i）将第一终端阻抗耦合到数据线，同时写入数据存在于数据输入端 如果信息指示要在存储器件内接收写入数据，或者（ii）在存储器件的数据输入端存在写数据时将第二终端阻抗耦合到数据线，如果 信息表示不在存储器件内接收写入数据。

公开(公告)号：US20070279084A1

公开(公告)日：2007-12-06

申请号：US11422022

申请日：2006-06-02

申请人： Kyung Suk Oh ,  Ian P. Shaeffer

发明人： Kyung Suk Oh ,  Ian P. Shaeffer

IPC分类号： H03K19/003

CPC分类号： H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

摘要： An integrated circuit device having graduated on-die termination. The integrated circuit device includes an input to receive a data signal, and first and second termination circuits. The first termination circuit includes a first load element and a first switch element to switchably couple the first load element to the data signal input. The second termination circuit includes a second load element and a second switch element to switchably couple the second load element to the data signal input.

摘要翻译： 集成电路器件，具有刻度上的片上端接。 集成电路装置包括用于接收数据信号的输入端以及第一和第二终端电路。 第一终端电路包括第一负载元件和第一开关元件，以将第一负载元件可切换地耦合到数据信号输入端。 第二终端电路包括第二负载元件和第二开关元件，以将第二负载元件可切换地耦合到数据信号输入端。

公开(公告)号：US06664482B1

公开(公告)日：2003-12-16

申请号：US09561591

申请日：2000-05-01

申请人： Ian P. Shaeffer ,  Everett Basham ,  Christopher D. Price

发明人： Ian P. Shaeffer ,  Everett Basham ,  Christopher D. Price

IPC分类号： H05K111

CPC分类号： H05K3/3484 ,  H01R31/08 ,  H05K1/0293 ,  H05K3/1216 ,  H05K2201/0305 ,  H05K2203/043 ,  H05K2203/173

摘要： A method of fabricating a zero signal degradation solder bridge electrical connection for connecting adjacent conducting pads of a printed circuit board, and a printed circuit board having at least one of these solder bridge electrical connections. In the method, a stencil, having an opening that corresponds to the adjacent conducting pads and at least a portion of the surface area of the printed circuit board between the adjacent conducting pads, is placed on the surface of printed circuit board. Solder paste is then applied to the stencil such that the solder paste flows through the stencil opening and onto the adjacent conducting pads and at least a portion of the surface area of the printed circuit board between the pads. The stencil is then removed and the printed circuit board is subjected to reflow soldering, thereby fabricating a printed circuit board having a solder bridge electrical connector between adjacent conducting pads.

摘要翻译： 一种制造用于连接印刷电路板的相邻导电焊盘的零信号劣化焊桥电连接的方法以及具有这些焊桥电连接中的至少一个的印刷电路板。 在该方法中，将具有对应于相邻导电焊盘的开口和相邻导电焊盘之间的印刷电路板的表面区域的至少一部分的模板放置在印刷电路板的表面上。 然后将焊膏施加到模板上，使得焊膏流过模板开口并且流到衬垫之间的相邻导电焊盘和印刷电路板的表面区域的至少一部分。 然后去除模版，并且对印刷电路板进行回流焊接，从而制造在相邻导电焊盘之间具有焊料桥电连接器的印刷电路板。

公开(公告)号：US06587965B1

公开(公告)日：2003-07-01

申请号：US09563004

申请日：2000-04-29

申请人： Ian P. Shaeffer ,  Jeffrey C. Swanson

发明人： Ian P. Shaeffer ,  Jeffrey C. Swanson

IPC分类号： G06F1100

CPC分类号： G01R31/31713 ,  G01R31/31705 ,  G06F11/25

摘要： The present invention provides for a method and system for external observation of a dual mode control interface, via a single point of entry/exit from a chip. In operation, data is sent into and retrieved from a chip using a single point on the chip. Multiple test methods can be used with the proper test method selected by an established hierarchy of methods. In one embodiment, an impedance is shown for control purposes between test methods.

摘要翻译： 本发明提供了一种用于通过单个进入/离开点从芯片外部观察双模式控制接口的方法和系统。 在操作中，使用芯片上的单个点将数据发送到芯片并从芯片检索。 可以通过建立的方法层次结构选择适当的测试方法来使用多种测试方法。 在一个实施例中，示出了用于测试方法之间的控制目的的阻抗。