公开(公告)号：US09479464B1

公开(公告)日：2016-10-25

申请号：US12423690

申请日：2009-04-14

申请人： Chi-Lie Wang ,  BaoDong Hu ,  Scott W. Mitchell

发明人： Chi-Lie Wang ,  BaoDong Hu ,  Scott W. Mitchell

IPC分类号： H04L12/28 ,  H04L12/879 ,  H04L29/06 ,  H04L12/861

CPC分类号： H04L49/901 ,  H04L49/9042 ,  H04L49/9063 ,  H04L63/02 ,  H04L69/22

摘要： A data processing system adapted for high-speed network communications, a method for managing a network interface and a network interface for such system, are provided, in to which processing of packets received over the network is achieved by embedded logic at the network interface level. Incoming packets on the network interface are parsed and classified as they are stored in a buffer memory. Functional logic coupled to the buffer memory on the network interface is enabled to access any data field within a packet in a single cycle, using pointers and packet classification information produced by the parsing and classifying step. Results of operations on the data fields in the packets are available before the packets are transferred out of the buffer memory. A data processing system, a method for management of a network interface and a network interface are also provided by the present invention that include an embedded firewall at the network interface level of the system, which protects against inside and outside attacks on the security of data processing system. Furthermore, a data processing system, a method for management of a network interface and a network interface are a provided by the present invention that support class of service management for packets incoming from the network, by applying priority rules at the network interface level of the system.

摘要翻译： 提供了适用于高速网络通信的数据处理系统，用于管理这种系统的网络接口和网络接口的方法，通过网络接收的分组的处理通过网络接口层的嵌入式逻辑来实现 。 网络接口上的传入数据包被解析和分类，因为它们存储在缓冲存储器中。 耦合到网络接口上的缓冲存储器的功能逻辑能够使用由解析和分类步骤产生的指针和分组分类信息在单个周期内访问分组内的任何数据字段。 在数据包从缓冲存储器传出之前，数据包中的数据字段的操作结果是可用的。 本发明还提供了一种数据处理系统，网络接口管理方法和网络接口，该系统包括在系统的网络接口层的嵌入式防火墙，可防止内部和外部对数据安全的攻击 处理系统。 此外，本发明提供了一种数据处理系统，网络接口管理方法和网络接口，其通过在网络接口级别应用优先级规则来支持从网络进入的分组的服务管理类别 系统。

公开(公告)号：US08332554B2

公开(公告)日：2012-12-11

申请号：US13172298

申请日：2011-06-29

申请人： Baranitharan Subbiah ,  Sanjay Katabathuni ,  Shoby A. Cherian ,  Chi-Lie Wang ,  Maria Hu ,  Sudhakar Rao ,  Kap Soh ,  Scott W. Mitchell ,  Raymond Su ,  Lomberto P. Jimenez

发明人： Baranitharan Subbiah ,  Sanjay Katabathuni ,  Shoby A. Cherian ,  Chi-Lie Wang ,  Maria Hu ,  Sudhakar Rao ,  Kap Soh ,  Scott W. Mitchell ,  Raymond Su ,  Lomberto P. Jimenez

IPC分类号： G06F13/12 ,  G06F3/00 ,  G06F15/173 ,  G06F15/16

CPC分类号： H04L29/06068 ,  H04L29/06 ,  H04L29/12254 ,  H04L61/2038 ,  H04L69/08 ,  H04L69/324

摘要： In one embodiment of a networking module, a first block receives a serial digital media signal, and provides a parallel digital media signal based on the serial digital media signal. A second block, operative with the first block, stores the parallel digital media signal in a corresponding slot in an outgoing frame, and sends the outgoing frame in response to receiving an incoming frame.

摘要翻译： 在网络模块的一个实施例中，第一块接收串行数字媒体信号，并且基于串行数字媒体信号提供并行数字媒体信号。 与第一块操作的第二块将并行数字媒体信号存储在输出帧中的相应时隙中，并且响应于接收到的帧而发送输出帧。

公开(公告)号：US20120057751A1

公开(公告)日：2012-03-08

申请号：US13258476

申请日：2009-09-24

申请人： Ke-Yan Liu ,  Liang Tang ,  Lie Wang ,  Wei Liu

发明人： Ke-Yan Liu ,  Liang Tang ,  Lie Wang ,  Wei Liu

IPC分类号： G06K9/00

CPC分类号： H04N7/18 ,  G06T7/277

摘要： A method for tracking an object in a video data, comprises the steps of determining a plurality of particles for estimating a location of the object in the video data, determining a weight for each of the plurality of the particles, wherein the weights of two or more particles are determined substantially in parallel, and estimating the location of the object in the video data based upon the determined particle weights.

摘要翻译： 一种用于跟踪视频数据中的对象的方法，包括以下步骤：确定用于估计视频数据中对象的位置的多个粒子，确定多个粒子中的每一个的权重，其中两个或 基本上并行地确定更多的粒子，并且基于所确定的粒子权重来估计视频数据中对象的位置。

公开(公告)号：US07996588B2

公开(公告)日：2011-08-09

申请号：US10449816

申请日：2003-05-30

申请人： Baranitharan Subbiah ,  Sanjay Katabathuni ,  Shoby A. Cherian ,  Chi-Lie Wang ,  Maria Hu ,  Sudhakar Rao ,  Kap Soh ,  Scott W. Mitchell ,  Raymond Su ,  Lomberto P. Jimenez

发明人： Baranitharan Subbiah ,  Sanjay Katabathuni ,  Shoby A. Cherian ,  Chi-Lie Wang ,  Maria Hu ,  Sudhakar Rao ,  Kap Soh ,  Scott W. Mitchell ,  Raymond Su ,  Lomberto P. Jimenez

IPC分类号： G06F13/12 ,  G06F3/00 ,  G06F15/173 ,  G06F15/16

CPC分类号： H04L29/06068 ,  H04L29/06 ,  H04L29/12254 ,  H04L61/2038 ,  H04L69/08 ,  H04L69/324

摘要： In one embodiment of a networking module, a first block receives a serial digital media signal, and provides a parallel digital media signal based on the serial digital media signal. A second block, operative with the first block, stores the parallel digital media signal in a corresponding slot in an outgoing frame, and sends the outgoing frame in response to receiving an incoming frame.

摘要翻译： 在网络模块的一个实施例中，第一块接收串行数字媒体信号，并且基于串行数字媒体信号提供并行数字媒体信号。 与第一块操作的第二块将并行数字媒体信号存储在输出帧中的相应时隙中，并且响应于接收到的帧而发送输出帧。

公开(公告)号：US07860120B1

公开(公告)日：2010-12-28

申请号：US09916715

申请日：2001-07-27

申请人： Chi-Lie Wang ,  Li-Jau Yang ,  Kap Soh ,  Chin-Li Mou

发明人： Chi-Lie Wang ,  Li-Jau Yang ,  Kap Soh ,  Chin-Li Mou

IPC分类号： H04L12/56

CPC分类号： H04L49/9052 ,  H04L47/6215 ,  H04L49/9005

摘要： A plurality of virtual paths in a network interface between a host port and a network port are managed according to respective priorities using dynamic buffer allocation. Thus, multiple levels of quality of service are supported through a single physical network port. Variant processes are applied for handling packets which have been downloaded to a network interface, prior to transmission onto the network. The network interface also includes memory used as a transmit buffer, that stores data packets received from the host computer on the first port, and provides data to the second port for transmission on the network. A control circuit in the network interface manages the memory as a plurality of first-in-first-out FIFO queues having respective priorities. Logic places a packet received from the host processor into one of the plurality of FIFO queues according to a quality of service parameter associated with the packets. Logic transmits the packets in the plurality of FIFO queues according to respective priorities. Logic dynamically allocates the memory using a list of buffer descriptors for corresponding buffers in said memory. The list of buffer descriptors comprises a free buffer list and a used buffer list for each of the virtual paths served by the system. A used buffer descriptor is released from the used buffer list, after the data stored in the corresponding used buffer has been transmitted, to the free buffer list for a virtual path which has the largest amount traffic or which has the smallest number of free buffers in its free buffer list.

摘要翻译： 在主机端口和网络端口之间的网络接口中的多个虚拟路径根据各自的优先级使用动态缓冲器分配进行管理。 因此，通过单个物理网络端口支持多级服务质量。 在传输到网络之前，应用变体过程来处理已经下载到网络接口的分组。 网络接口还包括用作发送缓冲器的存储器，其将从主计算机接收的数据分组存储在第一端口上，并且向第二端口提供数据以在网络上传输。 网络接口中的控制电路将存储器作为具有各自优先级的多个先进先出FIFO队列进行管理。 根据与分组相关联的服务质量参数，逻辑将从主机处理器接收到的分组放置在多个FIFO队列中的一个中。 逻辑根据各自的优先级传输多个FIFO队列中的分组。 逻辑使用所述存储器中的相应缓冲器的缓冲器描述符列表动态地分配存储器。 缓冲器描述符的列表包括由系统服务的每个虚拟路径的空闲缓冲器列表和使用的缓冲器列表。 在使用缓冲区列表中释放已使用的缓冲区描述符后，将存储在相应的已用缓冲区中的数据发送到具有最大数量流量或具有最小数量的可用缓冲区的虚拟路径的空闲缓冲区列表中 其免费缓冲列表。

公开(公告)号：US07818470B2

公开(公告)日：2010-10-19

申请号：US11863192

申请日：2007-09-27

申请人： Chi-Lie Wang ,  Jason Z. Mo ,  Bertan Tezcan

发明人： Chi-Lie Wang ,  Jason Z. Mo ,  Bertan Tezcan

IPC分类号： G06F3/00

CPC分类号： H04L47/28 ,  H04L47/30 ,  H04L47/33 ,  H04L49/90

摘要： A serial buffer is configured to transmit a plurality of received data packets through a data packet transfer path to a host processor. A doorbell controller of the serial buffer monitors the number of data packets transmitted to the host processor through the data packet transfer path, and estimates the number of data packets actually received by the host processor. The doorbell controller generates a doorbell command each time that the estimated number of data packets corresponds with a fixed number of data packets in a frame. The doorbell commands are transmitted to the host processor on a doorbell command path, which is faster than the data packet transfer path. The doorbell controller may estimate the number of data packets actually received by the host processor in response to a first delay value, which represents how much faster the doorbell command path is than the data packet transfer path.

摘要翻译： 串行缓冲器被配置为通过数据分组传送路径将多个接收到的数据分组发送到主机处理器。 串行缓冲器的门铃控制器通过数据包传送路径监视发送到主机处理器的数据包的数量，并估计主机处理器实际接收到的数据包的数量。 门铃控制器每当估计的数据分组数与帧中的固定数量的数据分组对应时，就产生门铃命令。 门铃命令在门铃命令路径上传送到主机处理器，该命令路径比数据包传送路径快。 门铃控制器可以响应于第一延迟值来估计主机处理器实际接收的数据分组的数量，其表示门铃命令路径比数据分组传送路径多得多的速度。

公开(公告)号：US07617346B2

公开(公告)日：2009-11-10

申请号：US11679823

申请日：2007-02-27

申请人： Chi-Lie Wang ,  Kwong Hou Mak ,  Jason Z. Mo

发明人： Chi-Lie Wang ,  Kwong Hou Mak ,  Jason Z. Mo

IPC分类号： G06F13/26

CPC分类号： G06F9/30094

摘要： Status/error reporting is implemented using a doorbell system. A plurality of flag registers are included on a system device, such as a serial buffer. Each flag register has a corresponding address, and stores a plurality of flags. A flag scan controller accesses the flag registers in a predetermined priority order, using the flag register addresses. Upon detecting that one or more of the flags of a flag register are activated, the flag scan controller causes a doorbell command to be generated. The doorbell command includes the flag register address and the corresponding flags. A system processor receives the doorbell command and services the activated flags. Once the activated flags are serviced, the system processor performs one or more software write operations to clear the flags within the system device. The system processor can simultaneously service multiple flags. The system processor can also simultaneously clear multiple flags.

摘要翻译： 使用门铃系统实现状态/错误报告。 多个标志寄存器被包括在诸如串行缓冲器的系统设备上。 每个标志寄存器具有对应的地址，并存储多个标志。 标志扫描控制器使用标志寄存器地址以预定的优先级顺序访问标志寄存器。 在检测到标志寄存器的一个或多个标志被激活时，标志扫描控制器产生门铃命令。 门铃命令包括标志寄存器地址和相应的标志。 系统处理器接收门铃命令并服务激活的标志。 一旦激活的标志被服务，系统处理器执行一个或多个软件写入操作来清除系统设备内的标志。 系统处理器可以同时维护多个标志。 系统处理器还可以同时清除多个标志。

公开(公告)号：US20090228630A1

公开(公告)日：2009-09-10

申请号：US12043943

申请日：2008-03-06

申请人： Chi-Lie Wang ,  Jason Z. Mo

发明人： Chi-Lie Wang ,  Jason Z. Mo

IPC分类号： G06F12/00

CPC分类号： H04L49/9047 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9036

摘要： Within a serial buffer, request packets are written to available memory blocks of a memory buffer, which are identified by a free buffer pointer list. When a request packet is written to a memory block, the memory block is removed from the free buffer pointer list, and added to a used buffer pointer list. Memory blocks in the used buffer pointer list are read, thereby transmitting the associated request packets from the serial buffer. When a request packet is read from a memory block, the memory block is removed from the used buffer pointer list and added to a request buffer pointer list. If a corresponding response packet is received within a timeout period, the memory block is transferred from the request buffer pointer list to the free buffer pointer list. Otherwise, the memory block is transferred from the request buffer pointer list to the used buffer pointer list.

摘要翻译： 在串行缓冲器中，请求数据包被写入存储器缓冲器的可用存储器块，这些存储器块由空闲缓冲器指针列表标识。 当请求数据包被写入存储器块时，存储块从空闲缓冲区指针列表中移除，并被添加到使用的缓冲区指针列表中。 读取所使用的缓冲器指针列表中的存储器块，从而从串行缓冲器发送关联的请求包。 当从存储器块读取请求数据包时，从使用的缓冲区指针列表中删除存储器块，并将其添加到请求缓冲区指针列表中。 如果在超时时段内接收到相应的响应包，则将该存储器块从请求缓冲区指针列表传送到空闲缓冲区指针列表。 否则，内存块从请求缓冲区指针列表传输到使用的缓冲区指针列表。

公开(公告)号：US20090225775A1

公开(公告)日：2009-09-10

申请号：US12043934

申请日：2008-03-06

申请人： Chi-Lie Wang ,  Jason Z. Mo

发明人： Chi-Lie Wang ,  Jason Z. Mo

IPC分类号： H04J3/22

CPC分类号： H04L47/30 ,  H04L49/90 ,  H04L69/08

摘要： A serial buffer includes a first port configured to implement an serial rapid I/O (sRIO) protocol and a second port configured to implement a Lite-weight serial (Lite) protocol. SRIO packets received on the first port are translated into Lite request packets compatible with the Lite protocol. The Lite request packets are transmitted to the second port. Lite response packets compatible with the Lite protocol are returned to the second port in response to the Lite request packets. The Lite response packets are translated into sRIO response packets compatible with the sRIO protocol. These sRIO response packets are returned to the first port, thereby providing a mechanism to acknowledge successful transmissions from the first port to the second port. Unsuccessful transmissions are identified by a timeout mechanism. The serial buffer also enables transfers from the second port to the first port in a similar manner.

摘要翻译： 串行缓冲器包括被配置为实现串行快速I / O（sRIO）协议的第一端口和被配置为实现Lite-weight串行（Lite）协议）的第二端口。 在第一个端口接收到的SRIO数据包被转换成与Lite协议兼容的Lite请求报文。 Lite请求数据包被传输到第二个端口。 与Lite协议兼容的Lite响应报文将返回到第二个端口，以响应Lite请求报文。 Lite响应数据包被转换为与sRIO协议兼容的sRIO响应数据包。 这些sRIO响应分组被返回到第一端口，从而提供一种机制来确认从第一端口到第二端口的成功传输。 不成功的传输通过超时机制来识别。 串行缓冲器还能够以类似的方式从第二端口传输到第一端口。

公开(公告)号：US07577857B1

公开(公告)日：2009-08-18

申请号：US09942789

申请日：2001-08-29

申请人： Nathan Henderson ,  Chi-Lie Wang ,  Baodong Hu

发明人： Nathan Henderson ,  Chi-Lie Wang ,  Baodong Hu

IPC分类号： G06F1/32

CPC分类号： G06F1/325 ,  G06F1/3203 ,  G06F1/3209 ,  Y02D30/32 ,  Y02D50/20

摘要： A computer system comprises host processor and a network interface, wherein the host processor includes resources supporting a full power mode, a lower power mode and a power down mode, as seen in standard system bus specifications such as PCI and InfiniBand. The network interface includes a medium interface unit coupled to network media supporting a least high speed protocol, such as a Gigabit Ethernet or high-speed InfiniBand, and a lower speed protocol, such as one of 10 Mb and 100 Mb Ethernet or a lower speed InfiniBand. Power management circuitry forces the medium interface unit to the lower speed protocol in response to an event signaling entry of the lower power mode. In the lower power mode, the network interface consumes less than the specified power when executing the lower speed protocol, and consumes greater than the specified power when executing the high speed protocol. Logic in the network interface operates in the lower power mode, and uses the lower speed protocol to detect a pattern in incoming packets. In response to the detection of said pattern, the logic issues a reset signal to the host processor. Thus, the network interface operates as a wake-up device in the lower power mode, using the lower speed protocol.

摘要翻译： 计算机系统包括主处理器和网络接口，其中主处理器包括支持全功率模式，较低功率模式和掉电模式的资源，如标准系统总线规范（如PCI和InfiniBand）所示。 网络接口包括耦合到支持最小高速协议（例如千兆以太网或高速InfiniBand）的网络媒体的介质接口单元和诸如10Mb和100Mb以太网之一或较低速度的低速协议 InfiniBand。 响应于较低功率模式的事件信号输入，电源管理电路强制介质接口单元进入低速协议。 在较低功率模式下，执行低速协议时，网络接口消耗的功率小于指定功率，在执行高速协议时消耗大于指定功率。 网络接口中的逻辑工作在较低功耗模式，并使用较低速度协议来检测输入数据包中的模式。 响应于所述模式的检测，逻辑向主处理器发出复位信号。 因此，使用较低速度协议，网络接口作为较低功率模式的唤醒设备工作。