公开(公告)号：US07236412B2

公开(公告)日：2007-06-26

申请号：US11053659

申请日：2005-02-09

申请人： Manfred Pröll ,  Johann Pfeiffer ,  Stephan Schröder ,  Arndt Gruber ,  Georg Erhard Eggers

发明人： Manfred Pröll ,  Johann Pfeiffer ,  Stephan Schröder ,  Arndt Gruber ,  Georg Erhard Eggers

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C7/1006 ,  G11C11/401 ,  G11C29/36 ,  G11C29/50016 ,  G11C29/80

摘要： An integrated semiconductor memory including memory cells which can be driven via first and second word lines and can be replaced by redundant memory cells. In the first memory cell type, data can be stored corresponding to the data present at a data input terminal. In the memory cells of a second memory cell type, data can be stored inverted with respect to data present at the data input terminal. The integrated semiconductor memory includes a circuit for data inversion, wherein the data are written to a redundant memory cell, inverted with respect to the data present at the data input terminal if the defective memory cell and the redundant memory cell replacing it are situated in different word line strips of a bit line twist, and if the defective memory cell and the redundant memory cell replacing it are associated with different memory cell types.

摘要翻译： 一种集成半导体存储器，包括可以经由第一和第二字线驱动并可由冗余存储器单元代替的存储单元。 在第一存储单元类型中，可以对应于存在于数据输入端的数据存储数据。 在第二存储单元类型的存储单元中，数据可以相对于存在于数据输入端的数据反转存储。 集成半导体存储器包括用于数据反转的电路，其中数据被写入冗余存储单元，相对于存在于数据输入端的数据而被反转，如果有缺陷的存储单元和替换它的冗余存储单元位于不同的 位线的字线条扭曲，并且如果不良存储器单元和替换它的冗余存储器单元与不同的存储器单元类型相关联。

公开(公告)号：US20050174863A1

公开(公告)日：2005-08-11

申请号：US11053659

申请日：2005-02-09

申请人： Manfred Proll ,  Johann Pfeiffer ,  Stephan Schroder ,  Arndt Gruber ,  Georg Eggers

发明人： Manfred Proll ,  Johann Pfeiffer ,  Stephan Schroder ,  Arndt Gruber ,  Georg Eggers

IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C29/00 ,  G11C29/36 ,  G11C29/50

CPC分类号： G11C29/50 ,  G11C7/1006 ,  G11C11/401 ,  G11C29/36 ,  G11C29/50016 ,  G11C29/80

摘要： An integrated semiconductor memory including memory cells which can be driven via first and second word lines and can be replaced by redundant memory cells. In the first memory cell type, data can be stored corresponding to the data present at a data input terminal. In the memory cells of a second memory cell type, data can be stored inverted with respect to data present at the data input terminal. The integrated semiconductor memory includes a circuit for data inversion, wherein the data are written to a redundant memory cell, inverted with respect to the data present at the data input terminal if the defective memory cell and the redundant memory cell replacing it are situated in different word line strips of a bit line twist, and if the defective memory cell and the redundant memory cell replacing it are associated with different memory cell types.

摘要翻译： 一种集成半导体存储器，包括可以经由第一和第二字线驱动并可由冗余存储器单元代替的存储单元。 在第一存储单元类型中，可以对应于存在于数据输入端的数据存储数据。 在第二存储单元类型的存储单元中，数据可以相对于存在于数据输入端的数据反转存储。 集成半导体存储器包括用于数据反转的电路，其中数据被写入冗余存储单元，相对于存在于数据输入端的数据而被反转，如果有缺陷的存储单元和替换它的冗余存储单元位于不同的 位线的字线条扭曲，并且如果不良存储器单元和替换它的冗余存储器单元与不同的存储器单元类型相关联。

公开(公告)号：US06574647B1

公开(公告)日：2003-06-03

申请号：US09582163

申请日：2000-09-18

申请人： Johann Pfeiffer ,  Manfred Listopad

发明人： Johann Pfeiffer ,  Manfred Listopad

IPC分类号： G06F1710

CPC分类号： H04L5/06 ,  H03H7/46

摘要： The invention relates to a filter arrangement for separating analog or digital baseband signals, for example, POTS or ISDN signals and digital wideband signals, which are simultaneously transmitted on a two-wire line of a message transmission system. In accordance with an exemplary embodiment of the invention, the filter arrangement has a bi-directional low-pass filter (4) and a bi-directional high-pass filter (3). The low-pass filter (4) includes a first filter (6) with a first passband. The first filter (6) permits flow-through of direct current. A second filter (7) with a second passband is preferably arranged assembled by connecting the inputs and outputs of the first and second filters (6, 7) in parallel.

摘要翻译： 本发明涉及用于分离模拟或数字基带信号（例如POTS或ISDN信号和数字宽带信号）的滤波器装置，其在消息传输系统的双线线路上同时发送。 根据本发明的示例性实施例，滤波器装置具有双向低通滤波器（4）和双向高通滤波器（3）。 低通滤波器（4）包括具有第一通带的第一滤波器（6）。 第一个过滤器（6）允许直流电流通过。 具有第二通带的第二滤波器（7）优选地通过并联连接第一和第二滤波器（6,7）的输入和输出来组装。

公开(公告)号：US5297163A

公开(公告)日：1994-03-22

申请号：US708015

申请日：1991-06-03

申请人： Johann Pfeiffer

发明人： Johann Pfeiffer

IPC分类号： H04L1/20 ,  H04L25/03 ,  H04L25/49 ,  H04B1/38 ,  H04C5/16

CPC分类号： H04L25/4919 ,  H04L1/20 ,  H04L25/03057

摘要： The present invention relates to a method of using a modem for processing signals for signal transmission in the base band on a two-wire line. In order to reduce coupling to adjacent channels in the two-wire line, and to reduce effective line attenuation, it is proposed that the signal that is to be transmitted in a process of the above type be encoded such that each three transmit bits are combined to form a tri-bit, and one of eight discriminable sender levels for a main data channel are associated with each tri-bit, whereby the modulation rate of the symbols on the line is reduced to one-third of the bit rate.

摘要翻译： 本发明涉及一种使用调制解调器处理信号以在双线线路上的基带中进行信号传输的方法。 为了减少与双线线路中的相邻信道的耦合，并且为了减少有效的线路衰减，提出将要在上述类型的过程中发送的信号被编码，使得每三个发送比特被组合 以形成三位，并且主数据信道的八个可判别发送器电平之一与每个三位相关联，由此将线上的符号的调制率降低到比特率的三分之一。

公开(公告)号：US07135723B2

公开(公告)日：2006-11-14

申请号：US10810489

申请日：2004-03-26

申请人： Kazimierz Szczpinski ,  Johann Pfeiffer

发明人： Kazimierz Szczpinski ,  Johann Pfeiffer

IPC分类号： H01L29/76

CPC分类号： H01L22/34 ,  G01R31/2882 ,  G01R31/31701

摘要： An integrated circuit with a test circuit having a measurement converter circuit and an activation unit. The measurement converter circuit converts one or more circuit-internal signals into a measured value. The activation unit activates the measurement converter circuit in accordance with an activation signal. The measurement converter circuit and the activation unit are connected to a connection pad. The activation unit is configured in such a way as to switch on the measurement converter circuit by means of the activation signal received via the connection pad. The measured value can be tapped off via the connection pad.

摘要翻译： 一种具有测试电路的集成电路，具有测量转换器电路和激活单元。 测量转换器电路将一个或多个电路内部信号转换成测量值。 激活单元根据激活信号激活测量转换器电路。 测量转换器电路和激活单元连接到连接垫。 激活单元被配置为通过经由连接垫接收的激活信号来接通测量转换器电路。 测量值可以通过连接板进行分接。

公开(公告)号：US06989707B2

公开(公告)日：2006-01-24

申请号：US10419596

申请日：2003-04-21

申请人： Graf Albert Von Keyserlingk ,  Helmut Schneider ,  Johann Pfeiffer

发明人： Graf Albert Von Keyserlingk ,  Helmut Schneider ,  Johann Pfeiffer

IPC分类号： G05F11/16

CPC分类号： G11C29/027 ,  G11C17/16 ,  G11C17/18

摘要： A semiconductor circuit has at least one generator fuse for setting a supply voltage and at least one redundancy fuse for activating a redundancy element. A first read-out device is provided for reading out the generator fuse and a second read-out device reads out the redundancy fuse. The first read-out device is configured to read out the generator fuse at a first instant, and the second read-out device is configured to read out the redundancy fuse at a second instant.

公开(公告)号：US06982981B1

公开(公告)日：2006-01-03

申请号：US09857029

申请日：1999-12-01

申请人： Johann Pfeiffer

发明人： Johann Pfeiffer

IPC分类号： H04J3/24

CPC分类号： H04Q11/0478 ,  H04L2012/5615 ,  H04L2012/5648 ,  H04L2012/5651 ,  H04L2012/5658

摘要： The invention relates to a method for configuring a network termination unit for the packet-by-packet asynchronous transfer mode transmission of data. According to said method data subdivided into cells and assembled into packets are transmitted either at a constant data rate (CBR), for example in the case of voice or video data, or at a non-constant data rate (UBR). The data cells or packets are received and transmitted via the network termination unit, which constitutes an interface between a transmission line and data terminal. The number of data cells contained in each transmitted or received data packet is determined in the network unit (10) and from this number it is determined whether the ATM connection is carried out at a constant (CBR) or non-constant (UBR) data rate. The data packets of a CBR connection have processing priority over the data packets of a UBR connection.

摘要翻译： 本发明涉及一种用于配置用于逐个数据包异步传输模式传输数据的网络终端单元的方法。 根据所述方法，例如在语音或视频数据的情况下，或以非恒定数据速率（UBR），以细分为单元并且组装成分组的数据以恒定数据速率（CBR）发送。 通过网络终端单元接收并发送数据信元或数据包，构成传输线与数据终端之间的接口。 在网络单元（10）中确定每个发送或接收的数据分组中包含的数据单元的数量，并且从该数字确定是否以恒定（CBR）或非常数（UBR）数据执行ATM连接 率。 CBR连接的数据包比UBR连接的数据包具有处理优先级。

公开(公告)号：US06961273B2

公开(公告)日：2005-11-01

申请号：US11012927

申请日：2004-12-14

申请人： Sven Boldt ,  Johann Pfeiffer

发明人： Sven Boldt ,  Johann Pfeiffer

IPC分类号： G11C29/26 ,  G11C29/40 ,  G11C29/00

CPC分类号： G11C29/40 ,  G11C29/26 ,  G11C2029/2602

摘要： One embodiment of the invention provides a RAM memory circuit having k≧2 banks, each of which having a multiplicity of memory cells and a selection device to simultaneously select groups of in each case n≧2 memory cells of the bank for the writing or reading of n parallel data. For the fast testing of all the banks, devices are included for the parallel switching of the banks such that reading and writing may be effected simultaneously at all the banks. For each bank, a dedicated evaluation device is included for comparing the n data respectively read out at the relevant bank with a reference information item, which is representative of the write data which have previously been written in at the currently selected memory cell group of the bank, and for providing a result information item, comprising 1≦m≦n/k bits, each of which indicates whether a subset precisely assigned to it from m subsets of the n read data corresponds to a part of the reference information item which is precisely assigned to said subset.

摘要翻译： 本发明的一个实施例提供了一种RAM存储器电路，其具有k个= 2个存储体，每个存储体具有多个存储器单元和选择装置，用于在每种情况下同时选择用于写入的存储体的n个= 2个存储单元的组 或读取n个并行数据。 对于所有银行的快速测试，包括用于并行交换银行的设备，以便可以在所有银行同时进行阅读和书写。 对于每个存储体，包括一个专用的评估装置，用于比较在相关存储体上分别读出的n个数据与参考信息项目，该参考信息项目代表先前在当前选择的存储单元组中写入的写入数据 并且用于提供包括1 <= m <= n / k个比特的结果信息项，每个比特指示从n个读取数据的m个子集精确地分配给它的子集是否对应于参考信息项的一部分 其被精确地分配给所述子集。

公开(公告)号：US06859411B2

公开(公告)日：2005-02-22

申请号：US10623831

申请日：2003-07-21

申请人： Johann Pfeiffer ,  Helmut Fischer

发明人： Johann Pfeiffer ,  Helmut Fischer

IPC分类号： G11C11/408 ,  G11C11/4097 ,  G11C8/00

CPC分类号： G11C11/4097 ,  G11C11/4087

摘要： A method for writing and reading data is performed on a dynamic memory circuit. The memory circuit has memory cells that can be addressed via word lines and bit lines. A word line is activated in the event of addressing of a memory area with a specific address. A word line has a plurality of mutually separate word line sections. Via the bit lines, in the event of addressing with the specific address, in parallel, a first number of data can be written to memory cells addressed by the address or the first number of data can be read from memory cells addressed by the address. In the event of addressing with a specific address, only a portion of the word line sections are activated, in order that only a portion of the memory cells connected to the word line are written to in parallel or read from in parallel.

摘要翻译： 在动态存储器电路上执行用于写入和读取数据的方法。 存储器电路具有可通过字线和位线寻址的存储单元。 在使用特定地址寻址存储区域的情况下，字线被激活。 字线具有多个相互分离的字线部分。 通过位线，在与特定地址进行寻址的情况下，并行地将第一数量的数据写入由地址寻址的存储器单元，或者可以从地址寻址的存储单元读取第一数据数。 在使用特定地址进行寻址的情况下，只有一部分字线部分被激活，以便仅连接到字线的存储器单元的一部分被并行地并行地并行地读取。

公开(公告)号：US06711085B2

公开(公告)日：2004-03-23

申请号：US10266190

申请日：2002-10-07

申请人： Helmut Fischer ,  Johann Pfeiffer

发明人： Helmut Fischer ,  Johann Pfeiffer

IPC分类号： G11C800

CPC分类号： G11C11/4097 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4094

摘要： A digital memory circuit contains a plurality of areas each having memory cells disposed in matrix form in rows and columns. The columns of each memory area is subdivided into a plurality of adjacent groups which each form a segment. For each segment, provision is made of a separate set of two-conductor local data lines which lead via line switches to two-conductor master data lines common to all the memory areas. Furthermore, precharge devices are provided in order to equalize the potentials of the conductors of the local data lines and the conductors of the master data lines, the equalization potential for the local data lines being different than the equalization potential for the master data lines. A line switch control device provides for closing only of the line switches on those local data lines which belong to the segment in which a write or read mode takes place.

摘要翻译： 数字存储器电路包括多个区域，每个区域具有以行和列的矩阵形式设置的存储单元。 每个存储器区域的列被细分成多个相邻的组，每个组形成一个段。 对于每个段，提供一组单独的双导体本地数据线，其通过线路开关导通到所有存储区域共有的双导线主数据线。 此外，提供预充电装置以便均衡本地数据线的导体和主数据线的导体的电位，本地数据线的均衡电位与主数据线的均衡电位不同。 线路开关控制装置提供仅关闭属于发生写入或读取模式的段的那些本地数据线上的线路交换机。