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    Process for manufacturing integrated resistor and phase-change memory element including this resistor
    2.
    发明申请
    Process for manufacturing integrated resistor and phase-change memory element including this resistor 审中-公开
    集成电阻器和包括该电阻器的相变存储元件的制造工艺

    公开(公告)号：US20050269667A1

    公开(公告)日：2005-12-08

    申请号：US11201790

    申请日：2005-08-11

    申请人： Romina Zonca ,  Maria Marangon ,  Giorgio De Santi

    发明人： Romina Zonca ,  Maria Marangon ,  Giorgio De Santi

    IPC分类号： H01L45/00 ,  H01L29/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/008 ,  G11C2213/52 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

    摘要： A vertical-current-flow resistive element includes a monolithic region having a first portion and a second portion arranged on top of one another and formed from a single material. The first portion has a first resistivity, and the second portion has a second resistivity, lower than the first resistivity. To this aim, a monolithic region with a uniform resistivity and a height greater than at least one of the other dimensions is first formed; then the resistivity of the first portion is increased by introducing, from the top, species that form a prevalently covalent bond with the conductive material of the monolithic region, so that the concentration of said species becomes higher in the first portion than in the second portion. Preferably, the conductive material is a binary or ternary alloy, chosen from among TiAl, TiSi, TiSi2, Ta, WSi, and the increase in resistivity is obtained by nitridation.

    摘要翻译： 垂直电流阻力元件包括具有第一部分和第二部分的整体区域，第一部分和第二部分彼此顶部布置并由单一材料形成。 第一部分具有第一电阻率，第二部分具有低于第一电阻率的第二电阻率。 为此目的，首先形成具有均匀的电阻率和高于其它尺寸中的至少一个的高度的整体区域; 那么通过从顶部引入与整体区域的导电材料形成普遍共价键的物质来增加第一部分的电阻率，使得所述物质的浓度在第一部分中比在第二部分中更高 。 优选地，导电材料是选自TiAl，TiSi，TiSi 2，Ta，WSi的二元或三元合金，并且通过氮化获得电阻率的增加。

    Process for manufacturing a memory with local electrical contact between the source line and the well
    4.
    发明申请
    Process for manufacturing a memory with local electrical contact between the source line and the well 审中-公开
    用于制造在源极线和阱之间具有局部电接触的存储器的工艺

    公开(公告)号：US20060180850A1

    公开(公告)日：2006-08-17

    申请号：US11331826

    申请日：2006-01-12

    申请人： Daniela Brazzelli ,  Giorgio Servalli ,  Davide Erbetta ,  Maria Marangon

    发明人： Daniela Brazzelli ,  Giorgio Servalli ,  Davide Erbetta ,  Maria Marangon

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： A process for manufacturing a memory having a plurality of memory cells includes the steps of forming a well (having a first type of conductivity) within a wafer of semiconductor material, defining active regions within the well extending in a first direction, forming memory cells within the active regions (each memory cell having a source region with a second type of conductivity opposite to the first type of conductivity), and forming lines of electrical contact which electrically contact source regions aligned in a second direction. The step of forming lines of electrical contact includes forming an electrical contact between the source regions and portions of the well adjacent thereto in the second direction. The memory accordingly includes lines of electrical contact, each in electrical contact with source regions aligned along a respective row, wherein the lines of electrical contact further provide an electrical contact between the source regions and portions of the well adjacent thereto along said rows.

    摘要翻译： 一种用于制造具有多个存储单元的存储器的方法包括以下步骤：在半导体材料的晶片内形成阱（具有第一类型的导电性），限定在第一方向上延伸的阱内的有源区，形成存储单元内 有源区（每个存储单元具有与第一类型的导电性相反的第二类型的导电性的源极区），以及形成与第二方向对准的电接触的电接触线。 形成电接触线的步骤包括在第二方向上在源极区域和与其相邻的阱的部分之间形成电接触。 存储器相应地包括电接触线，每条电路与沿着相应行排列的源区电接触，其中电接触线还提供沿着所述行的源极区域和与其相邻的阱的部分之间的电接触。

    Manufacturing method of an integrated circuit formed on a semiconductor substrate
    5.
    发明申请
    Manufacturing method of an integrated circuit formed on a semiconductor substrate 审中-公开
    形成在半导体基板上的集成电路的制造方法

    公开(公告)号：US20080057682A1

    公开(公告)日：2008-03-06

    申请号：US11899275

    申请日：2007-09-04

    申请人： Camillo Bresolin ,  Davide Erbetta ,  Maria Marangon

    发明人： Camillo Bresolin ,  Davide Erbetta ,  Maria Marangon

    IPC分类号： H01L21/425 ,  H01L29/06

    CPC分类号： H01L21/31111 ,  H01L21/31144 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531

    摘要： An embodiment of a method for manufacturing an integrated circuit formed on a semiconductor substrate comprising the steps of: forming at least one shielding structure on said semiconductor substrate, forming a protective layer at least on portions of the semiconductor substrate that surround said shielding structure, carrying out a ionic implantation step with a tilt angle with respect to a normal to a plane defined by said semiconductor substrate so that said at least one shielding structure shields first portions of the protective layer, removing second portions of the protective layer that have been subjected to the ionic implant.

    摘要翻译： 一种形成在半导体衬底上的集成电路的制造方法的实施例，包括以下步骤：在所述半导体衬底上形成至少一个屏蔽结构，至少在半导体衬底的围绕所述屏蔽结构的部分上形成保护层，承载 离开注入步骤，其具有相对于由所述半导体衬底限定的平面的法线的倾斜角度，使得所述至少一个屏蔽结构屏蔽所述保护层的第一部分，去除所述保护层的已经经受的 离子植入物。

    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array thereby manufactured
    6.
    发明申请
    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array thereby manufactured 有权
    因此制造Cu-damascene技术和相变存储器阵列中的相变存储器阵列的制造方法

    公开(公告)号：US20070148814A1

    公开(公告)日：2007-06-28

    申请号：US11317622

    申请日：2005-12-22

    申请人： Fabio Pellizzer ,  Roberto Bez ,  Maria Marangon ,  Roberta Piva ,  Laura Aina

    发明人： Fabio Pellizzer ,  Roberto Bez ,  Maria Marangon ,  Roberta Piva ,  Laura Aina

    IPC分类号： H01L21/06

    CPC分类号： H01L45/1691 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    摘要： A process for manufacturing a phase change memory array includes the steps of: forming a plurality of phase change memory cells in an array region of a semiconductor wafer, the phase change memory cells arranged in rows and columns according to a row direction and to a column direction, respectively; forming a control circuit in a control region of the semiconductor wafer; forming a plurality of first bit line portions for mutually connecting phase change memory cells arranged on a same column; forming first level electrical interconnection structures; and forming second level electrical interconnection structures above the first level electrical interconnection structures. The first level electrical interconnection structures include second bit line portions laying on and in contact with the first bit line portions and projecting from the first bit line portions in the column direction for connecting the first bit line portions to the control circuit.

    摘要翻译： 一种相变存储器阵列的制造方法包括以下步骤：在半导体晶片的阵列区域中形成多个相变存储单元，根据行方向排列成行和列的相变存储单元和列 方向; 在所述半导体晶片的控制区域中形成控制电路; 形成多个第一位线部分，用于相互连接布置在同一列上的相变存储器单元; 形成一级电互连结构; 以及在所述第一级电互连结构之上形成第二级电互连结构。 第一级电互连结构包括布置在第一位线部分上并与第一位线部分接触的第二位线部分，并且在列方向上从第一位线部分突出以将第一位线部分连接到控制电路。