公开(公告)号：US07471218B2

公开(公告)日：2008-12-30

申请号：US11523131

申请日：2006-09-18

申请人： Mark D. Kuhns

发明人： Mark D. Kuhns

IPC分类号： H03M7/00

CPC分类号： H04N19/34 ,  H04N19/426

摘要： Various technologies for efficiently storing and retrieving streaming data are described. Bits of data (e.g., P bits of data) are received and separated into most significant bits (MSB) of data and least significant bits (LSB) of data. Further, the MSB of data and the LSB of data are respectively packed into a first word and a second word. The first word is stored in a first area of a frame buffer and the second word is stored in a second area of the frame buffer. As a result, data is managed in a more efficient way to reduce memory bandwidth requirement.

摘要翻译： 描述了用于有效地存储和检索流数据的各种技术。 数据位（例如，数据的P位）被接收并分离成数据的最高有效位（MSB）和数据的最低有效位（LSB）。 此外，数据的MSB和数据的LSB分别被包装成第一个字和第二个字。 第一个字被存储在帧缓冲器的第一区域中，第二个字被存储在帧缓冲器的第二个区域中。 因此，以更有效的方式管理数据以减少内存带宽需求。

公开(公告)号：US20080126823A1

公开(公告)日：2008-05-29

申请号：US11515238

申请日：2006-08-31

申请人： Mark D. Kuhns

发明人： Mark D. Kuhns

IPC分类号： G06F1/06

CPC分类号： H04L7/02 ,  H04L7/033

摘要： An embodiment of the present invention is directed to a circuit including a data relay stage configurable to receive primary data via a primary data interface, a primary clock having a frequency FP and a secondary clock having a frequency FS′. The primary data is received over a fixed periodic interval TI and at a rate substantially equal to FP. The amount of primary data received over TI is known to be N. The data relay stage is further configurable to provide secondary data via a secondary data interface based on the primary data and the secondary clock. The circuit also includes a phase-locked loop (PLL) circuit configurable to receive an interval reference signal having a frequency FI substantially equal to 1/TI. The PLL circuit is also configurable to provide the secondary clock based on the interval reference signal.

摘要翻译： 本发明的一个实施例涉及一种电路，其包括数据中继级，其可配置为经由主数据接口接收主数据，主时钟具有频率F P P和具有频率F的次时钟 。 主数据以固定的周期性间隔T I I和以基本上等于F P P的速率被接收。 已知T I接收的主数据量为N.数据中继级还可配置为通过次级数据接口基于主数据和辅助时钟提供辅助数据。 电路还包括锁相环（PLL）电路，其可配置为接收具有基本上等于1 / T I I的频率F I I的间隔参考信号。 PLL电路也可配置为基于间隔参考信号提供辅助时钟。

公开(公告)号：US20080069284A1

公开(公告)日：2008-03-20

申请号：US11523123

申请日：2006-09-18

申请人： Mark D. Kuhns ,  Daniel L. Simon

发明人： Mark D. Kuhns ,  Daniel L. Simon

IPC分类号： H03D3/24

CPC分类号： H03K5/1565 ,  G06F1/025 ,  H03K5/133 ,  H03K2005/00026 ,  H03L7/0805 ,  H03L7/0812

摘要： A system and method for performing output clock phase smoothing. A phase smoothing circuit is described and includes a numerically-controlled oscillator (NCO) configured to produce a plurality of NCO clock pulses at a selectable frequency that is based on an input clock. Edges of the plurality of NCO clock pulses are aligned to edges of the input clock. A phase error calculation module is coupled to the NCO and is configured to generate a corresponding phase error for each of the plurality of NCO clock pulses. A clock phase selectable delay is coupled to the phase error calculation module and is configured to adjust each of the plurality of NCO clock pulses according to the corresponding phase error to generate an output clock at the selectable frequency that are phase-adjusted to more closely match an ideal output clock phase. Edges of the output clock need not necessarily align to the edges of the input clock.

摘要翻译： 一种用于执行输出时钟相位平滑的系统和方法。 描述了相位平滑电路，并且包括被配置为以基于输入时钟的可选择频率产生多个NCO时钟脉冲的数控振荡器（NCO）。 多个NCO时钟脉冲的边缘与输入时钟的边缘对准。 相位误差计算模块耦合到NCO，并且被配置为针对多个NCO时钟脉冲中的每一个生成相应的相位误差。 时钟相位可选择延迟耦合到相位误差计算模块，并且被配置为根据对应的相位误差来调整多个NCO时钟脉冲中的每一个，以产生可选频率处的输出时钟，其被相位调整以更紧密匹配 理想的输出时钟相位。 输出时钟的边沿不一定与输入时钟的边沿对齐。

公开(公告)号：US20070285576A1

公开(公告)日：2007-12-13

申请号：US11449222

申请日：2006-06-07

申请人： Bruce C. Moore ,  Mark D. Kuhns

发明人： Bruce C. Moore ,  Mark D. Kuhns

IPC分类号： H04N5/202

CPC分类号： H04N5/202 ,  G09G3/20 ,  G09G3/2011 ,  G09G3/3611 ,  G09G2310/027 ,  G09G2320/0276 ,  G09G2320/066 ,  G09G2320/0673 ,  G09G2360/16 ,  G09G2370/08

摘要： A method and system for digitally scaling a waveform. A method is described performing a linear waveform transformation and translation of a curve in a smooth and continuous fashion. Another method is described for scaling a waveform in which the available accuracy and resolution is manipulated for a given waveform. Specifically, by strategically placing virtual tap points of a waveform, as well as changing the scaling factors used for calculating points on the waveform provides for adjusting the accuracy and resolution in one or more regions of a waveform. These scaling methods provide a digital equivalent of a voltage tap-based analog resistor ladder used for digital-to-analog conversion. The digital virtual tap points represent the analog voltage tap points, and the vertical translation of the curve acts in a smooth, monotonic, and continuous fashion.

摘要翻译： 一种用于数字缩放波形的方法和系统。 描述了以平滑且连续的方式执行曲线的线性波形变换和平移的方法。 描述了另一种方法来缩放波形，其中对于给定波形来操纵可用的精度和分辨率。 具体来说，通过策略性地放置波形的虚拟抽头点，以及改变用于计算波形上的点的缩放因子，用于调整波形的一个或多个区域的精度和分辨率。 这些缩放方法提供了数字等效的用于数模转换的基于电压抽头的模拟电阻梯。 数字虚拟抽头点表示模拟电压抽头点，曲线的垂直平移以平滑，单调和连续的方式起作用。

公开(公告)号：US07336268B1

公开(公告)日：2008-02-26

申请号：US10285243

申请日：2002-10-30

申请人： Donald E. Camp ,  Mark D. Kuhns ,  Randy J. Dahl ,  Osama F. Alborno

发明人： Donald E. Camp ,  Mark D. Kuhns ,  Randy J. Dahl ,  Osama F. Alborno

IPC分类号： G09G5/00

CPC分类号： G09G5/18 ,  G09G5/005

摘要： An exemplary point-to-point display system comprises a host system, a timing controller, and a display. The host system is configured to provide data for display. The timing controller is configurable to provide data swapping, bus swapping, bit swapping, and combinations thereof to provide arranged data in response to the provided data. The display is configured to display the arranged data.

摘要翻译： 示例性的点对点显示系统包括主机系统，定时控制器和显示器。 主机系统配置为提供数据进行显示。 定时控制器可配置为提供数据交换，总线交换，位交换及其组合，以响应所提供的数据提供排列的数据。 显示器被配置为显示排列的数据。

公开(公告)号：US07382349B1

公开(公告)日：2008-06-03

申请号：US10955991

申请日：2004-09-30

申请人： Mark D. Kuhns

发明人： Mark D. Kuhns

IPC分类号： G09G3/36

CPC分类号： G09G3/3685 ,  G09G2320/0252

摘要： A method of operating a display includes operating a pixel of the display using a first signal to provide a first brightness level. A characteristic of the first signal is represented by a value in a range extending from a minimum signal value to a maximum signal value. A second brightness level is then selected and is different from the first brightness level. A truncated table is consulted and contains overdrive values for selected pairs of possible first and second brightness levels. The overdrive values are in a range extending from a minimum table value to a maximum table value, where the minimum table value is less than the minimum signal value or the maximum table value is greater than the maximum signal value or both. An overdrive signal is determined from the overdrive values of the truncated table based on the first and second brightness levels. The pixel is briefly operated using the overdrive signal to facilitate transition to the second brightness level. The pixel is then operated using a second signal corresponding to the second brightness level.

摘要翻译： 操作显示器的方法包括使用第一信号来操作显示器的像素以提供第一亮度级。 第一信号的特性由从最小信号值到最大信号值的范围内的值表示。 然后选择第二亮度级别并且不同于第一亮度级别。 查看截断的表格，并包含可能的第一和第二亮度级别的选定对的超速值。 超速值在从最小表格值到最大表格值的范围内，其中最小表格值小于最小信号值，或者最大表格值大于最大信号值，或两者都是最大值。 基于第一和第二亮度级别从截断表的过驱动值确定过驱动信号。 使用过驱动信号来简单地操作像素，以便于转换到第二亮度级。 然后使用对应于第二亮度级的第二信号来操作像素。

公开(公告)号：US07826582B2

公开(公告)日：2010-11-02

申请号：US11523123

申请日：2006-09-18

申请人： Mark D. Kuhns ,  Daniel L. Simon

发明人： Mark D. Kuhns ,  Daniel L. Simon

IPC分类号： H03D3/24 ,  H04L7/00 ,  H03L7/06 ,  H03L7/00

CPC分类号： H03K5/1565 ,  G06F1/025 ,  H03K5/133 ,  H03K2005/00026 ,  H03L7/0805 ,  H03L7/0812

摘要： A system and method for performing output clock phase smoothing. A phase smoothing circuit is described and includes a numerically-controlled oscillator (NCO) configured to produce a plurality of NCO clock pulses at a selectable frequency that is based on an input clock. Edges of the plurality of NCO clock pulses are aligned to edges of the input clock. A phase error calculation module is coupled to the NCO and is configured to generate a corresponding phase error for each of the plurality of NCO clock pulses. A clock phase selectable delay is coupled to the phase error calculation module and is configured to adjust each of the plurality of NCO clock pulses according to the corresponding phase error to generate an output clock at the selectable frequency that are phase-adjusted to more closely match an ideal output clock phase. Edges of the output clock need not necessarily align to the edges of the input clock.

摘要翻译： 一种用于执行输出时钟相位平滑的系统和方法。 描述了相位平滑电路，并且包括被配置为以基于输入时钟的可选择频率产生多个NCO时钟脉冲的数控振荡器（NCO）。 多个NCO时钟脉冲的边缘与输入时钟的边缘对准。 相位误差计算模块耦合到NCO，并且被配置为针对多个NCO时钟脉冲中的每一个生成相应的相位误差。 时钟相位可选择延迟耦合到相位误差计算模块，并且被配置为根据相应的相位误差来调整多个NCO时钟脉冲中的每一个，以产生可选频率处的输出时钟，该输出时钟被相位调整以更紧密匹配 理想的输出时钟相位。 输出时钟的边沿不一定与输入时钟的边沿对齐。

公开(公告)号：US07317775B1

公开(公告)日：2008-01-08

申请号：US10892760

申请日：2004-07-16

申请人： Richard Alexander Erhart ,  Loren Tomasi ,  Mark D. Kuhns ,  Arif Alam

发明人： Richard Alexander Erhart ,  Loren Tomasi ,  Mark D. Kuhns ,  Arif Alam

IPC分类号： H04L7/00

CPC分类号： H04L7/0338 ,  H03L7/0807 ,  H03L7/0812

摘要： A method and circuit capable of handling skew between a clock and data signal up to +/− one half bit on a random input data pattern. A digital algorithm cycles through each data bit and individually deskews that bit by detecting data transitions in a first sampling region and in a second sampling region and determining a difference between a number of transitions in the first sampling region and a number of transitions in the second sampling region. The sampling regions and a deskew timing signal may then be incremented or decremented based on a comparison of the computed difference to a predetermined constant. If no transitions occur on a particular bit, the algorithm times out leaving the deskew timing signal in the original position. When analysis of a final bit of a channel is completed, the algorithm begins monitoring and analyzing the first bit of another channel.

摘要翻译： 一种能够在随机输入数据模式上处理高达+/- 1/2位的时钟和数据信号之间的偏差的方法和电路。 数字算法通过检测第一采样区域和第二采样区域中的数据转换，并且确定第一采样区域中的转换次数与第二采样区域中的转换次数之间的差异，循环遍历每个数据位，并单独地对该位进行偏移 采样区。 然后可以基于所计算的差异与预定常数的比较来增加或减少采样区域和去歪斜时序信号。 如果在特定位没有发生转换，则该算法超出了使偏移校正时间信号处于原始位置。 当分析通道的最终位完成时，算法开始监视和分析另一个通道的第一位。

公开(公告)号：US07882384B2

公开(公告)日：2011-02-01

申请号：US11515238

申请日：2006-08-31

申请人： Mark D. Kuhns

发明人： Mark D. Kuhns

IPC分类号： G06F1/00 ,  G06F3/00

CPC分类号： H04L7/02 ,  H04L7/033

摘要： An embodiment of the present invention is directed to a circuit including a data relay stage configurable to receive primary data via a primary data interface, a primary clock having a frequency FP and a secondary clock having a frequency FS′. The primary data is received over a fixed periodic interval TI and at a rate substantially equal to FP. The amount of primary data received over TI is known to be N. The data relay stage is further configurable to provide secondary data via a secondary data interface based on the primary data and the secondary clock. The circuit also includes a phase-locked loop (PLL) circuit configurable to receive an interval reference signal having a frequency FI substantially equal to 1/TI. The PLL circuit is also configurable to provide the secondary clock based on the interval reference signal.

摘要翻译： 本发明的实施例涉及一种包括数据中继级的电路，可配置为经由主数据接口接收主数据，具有频率FP的主时钟和具有频率FS'的辅时钟。 主要数据在固定的周期性间隔TI内以基本上等于FP的速率接收。 通过TI接收的主数据量已知为N.数据中继级还可配置为通过次级数据接口基于主数据和辅助时钟提供辅助数据。 电路还包括锁相环（PLL）电路，可配置为接收具有基本上等于1 / TI的频率FI的间隔参考信号。 PLL电路也可配置为基于间隔参考信号提供辅助时钟。

公开(公告)号：US07783105B2

公开(公告)日：2010-08-24

申请号：US11449222

申请日：2006-06-07

申请人： Bruce C. Moore ,  Mark D. Kuhns

发明人： Bruce C. Moore ,  Mark D. Kuhns

IPC分类号： G06K9/00

CPC分类号： H04N5/202 ,  G09G3/20 ,  G09G3/2011 ,  G09G3/3611 ,  G09G2310/027 ,  G09G2320/0276 ,  G09G2320/066 ,  G09G2320/0673 ,  G09G2360/16 ,  G09G2370/08

摘要： A method and system for digitally scaling a waveform. A method is described performing a linear waveform transformation and translation of a curve in a smooth and continuous fashion. Another method is described for scaling a waveform in which the available accuracy and resolution is manipulated for a given waveform. Specifically, by strategically placing virtual tap points of a waveform, as well as changing the scaling factors used for calculating points on the waveform provides for adjusting the accuracy and resolution in one or more regions of a waveform. These scaling methods provide a digital equivalent of a voltage tap-based analog resistor ladder used for digital-to-analog conversion. The digital virtual tap points represent the analog voltage tap points, and the vertical translation of the curve acts in a smooth, monotonic, and continuous fashion.

摘要翻译： 一种用于数字缩放波形的方法和系统。 描述了以平滑且连续的方式执行曲线的线性波形变换和平移的方法。 描述了另一种方法来缩放波形，其中对于给定波形来操纵可用的精度和分辨率。 具体来说，通过策略性地放置波形的虚拟抽头点，以及改变用于计算波形上的点的缩放因子，用于调整波形的一个或多个区域的精度和分辨率。 这些缩放方法提供了数字等效的用于数模转换的基于电压抽头的模拟电阻梯。 数字虚拟抽头点表示模拟电压抽头点，曲线的垂直平移以平滑，单调和连续的方式起作用。