Vertical cavity surface emitting laser array and a process for making same

    公开(公告)号:US06560262B1

    公开(公告)日:2003-05-06

    申请号:US09370667

    申请日:1999-08-09

    IPC分类号: H01S5183

    摘要: An array of VCSEL devices and a process for fabricating the VCSEL array is disclosed. The VCSEL array emits light at n different wavelengths, wherein n is at least two. A first portion of the VCSEL devices in the array emits light at a first wavelength and a second portion of the VCSEL devices emits light at a second wavelength. Each VCSEL device has an active region consisting of alternating bands of quantum wells and boundary layers bounded by top and bottom separate confinement layers. The active region is bounded by top and bottom mirrors. The length of the active region of the VCSEL devices that emit light at the first wavelength, &lgr;s1, is different from the length of the active region of the VCSEL devices that emit light at a second wavelength. The array is fabricated by forming successive layers of material on a III-V semiconductor substrate. The composition and dimensions of the individual devices are first determined from the desired emission wavelength, &lgr;sn, of the devices in the array. Devices that emit at wavelength &lgr;s1 have an active region with length L1. Devices that emit at wavelength &lgr;s2 have an active region with length L2. From this information, the desired difference in the length of the active regions of the devices in the array that emit at different wavelengths, &Dgr;L, is determined. In addition, the thickness and composition for the individual quantum well layers is determined such that the peak in the optical gain will be achieved at the desired wavelength for each device. Array fabrication is commenced by depositing at least one layer having uniform composition and thickness on the III-V substrate. An oxide mask is formed on the at least one layer of uniform thickness. The oxide mask is a pattern of oxide pads that are used to control the MOCVD growth rate and the composition of III-V semiconductor material subsequently formed thereon. The oxide mask pattern is selected to provide a layer of III-V semiconductor material that meets the composition and dimension specifications for the devices in the array. After the desired pattern is determined, and the oxide pads are formed, a III-V semiconductor material is formed on the substrate by MOCVD. During the growth step, the quantum well layers of the desired thickness and composition are formed. The growth is continued until the desired &Dgr;L is obtained. MOCVD is then stopped and the oxide mask is removed. A layer of III-V semiconductor material having uniform composition and thickness is then deposited on the structure. This deposition step continues until sufficient material is deposited on the structure from which to form an array of devices having active regions with the desired Ln. A layer of material having uniform composition that will become the top mirror of the VCSEL devices is then deposited on the structure. The desired devices are then etched from the desired structure.

    Process for fabricating an optical waveguide
    4.
    发明授权
    Process for fabricating an optical waveguide 失效
    光波导制造工艺

    公开(公告)号:US06261857B1

    公开(公告)日:2001-07-17

    申请号:US09097924

    申请日:1998-06-17

    IPC分类号: H01L2100

    摘要: A process for fabricating a waveguide with a desired tapered profile is disclosed. The waveguide has a first section with a first height and a second section with a second height. The first height is greater than the second height. The waveguide height tapers from the first height to the second height. The waveguide is a compound semiconductor material and is formed using selective area growth. In selective area growth, a dielectric mask is formed on a substrate. The dimensions of the dielectric mask are selected to provide a waveguide with the desired dimensions. The compound semiconductor material is deposited on the substrate using chemical vapor deposition. The dielectric mask affects the rate at which the compound material is deposited in areas of the substrate proximate to the mask. Therefore, the profile of the waveguide formed using the selected mask dimensions is modeled and compared with the desired profile. If modeled profile is not acceptably similar to the desired profile, the dimensions of the mask are modified. The profile of the waveguide formed using the modified mask dimensions is again modeled, and the modeled waveguide profile is compared with the desired waveguide profile. This process is repeated until the modeled profile is sufficiently similar to the desired profile. After the mask dimensions are selected, the mask is formed on the substrate, and the compound semiconductor waveguide is formed on the substrate using selective area growth.

    摘要翻译: 公开了一种制造具有所需锥形轮廓的波导的方法。 波导具有具有第一高度的第一部分和具有第二高度的第二部分。 第一个高度大于第二个高度。 波导高度从第一高度向第二高度逐渐变细。 波导是化合物半导体材料,并且使用选择性面积生长形成。 在选择性区域生长中,在基板上形成介电掩模。 选择介电掩模的尺寸以提供具有期望尺寸的波导。 使用化学气相沉积将化合物半导体材料沉积在基板上。 介电掩模影响复合材料沉积在靠近掩模的基板的区域中的速率。 因此,使用所选择的掩模尺寸形成的波导的轮廓被建模并与期望的轮廓进行比较。 如果建模的轮廓不可接受地类似于所需的轮廓,则掩模的尺寸被修改。 再次对使用修改的掩模尺寸形成的波导的轮廓进行建模,并将所建模的波导轮廓与期望的波导轮廓进行比较。 重复该过程,直到建模的轮廓与期望的轮廓充分相似。 在选择掩模尺寸之后,在基板上形成掩模,并且使用选择性区域生长在基板上形成化合物半导体波导。

    Photoreflectance spectral analysis of semiconductor laser structures
    5.
    发明授权
    Photoreflectance spectral analysis of semiconductor laser structures 有权
    半导体激光器结构的光反射光谱分析

    公开(公告)号:US06195166B1

    公开(公告)日:2001-02-27

    申请号:US09305712

    申请日:1999-05-05

    IPC分类号: G01N2155

    CPC分类号: G01N21/1717

    摘要: A micro-photoreflectance technique has been developed for performing non-destructive analysis of III-V optoelectronic devices. By using a significantly reduced spot size (for example, 10 micrometers), various compositional features of the device may be analyzed and the Franz-Keldysh oscillations appearing in the micro-photoreflectance wavelength spectra (such as those beyond the barrier/SCL wavelength in an EML structure) may be analyzed to provide information regarding the physical characteristics of the device, such as the electric field and p-i junction placement within an exemplary EML device structure.

    摘要翻译: 已经开发了用于对III-V光电子器件进行非破坏性分析的微光反射技术。 通过使用显着减小的光斑尺寸(例如,10微米),可以分析器件的各种组成特征,并且出现在微光反射波长光谱中的Franz-Keldysh振荡(例如,在 EML结构)可以被提供关于装置的物理特征的信息,例如示例性EML装置结构内的电场和pi结布置。