摘要:
The present invention provides an optoelectronic device, a method of manufacture thereof, and an optical communication system including the same. The optoelectronic device may include, in one particular embodiment, an active device located over a substrate and a passive device located proximate the active device and over the substrate. The optoelectronic device may further include a doped cladding layer located over the active and passive devices and a barrier layer located over the doped cladding layer and the passive device.
摘要:
A method for decreasing the diffusion of dopant atoms in the active region, as well as the interdiffuision of different types of dopant atoms among adjacent doped regions, of optoelectronic devices is disclosed. The method of the present invention employs a plurality of InAlAs and/or InGaAlAs layers to avoid the direct contact between the dopant atoms and the active region, and between the dopant atoms in adjacent blocking structures of optoelectronic devices. A semi-insulating buried ridge structure, as well as a ridge structure, in which the interdiffusion of different types of dopant atoms is suppressed are also disclosed.
摘要:
An array of VCSEL devices and a process for fabricating the VCSEL array is disclosed. The VCSEL array emits light at n different wavelengths, wherein n is at least two. A first portion of the VCSEL devices in the array emits light at a first wavelength and a second portion of the VCSEL devices emits light at a second wavelength. Each VCSEL device has an active region consisting of alternating bands of quantum wells and boundary layers bounded by top and bottom separate confinement layers. The active region is bounded by top and bottom mirrors. The length of the active region of the VCSEL devices that emit light at the first wavelength, &lgr;s1, is different from the length of the active region of the VCSEL devices that emit light at a second wavelength. The array is fabricated by forming successive layers of material on a III-V semiconductor substrate. The composition and dimensions of the individual devices are first determined from the desired emission wavelength, &lgr;sn, of the devices in the array. Devices that emit at wavelength &lgr;s1 have an active region with length L1. Devices that emit at wavelength &lgr;s2 have an active region with length L2. From this information, the desired difference in the length of the active regions of the devices in the array that emit at different wavelengths, &Dgr;L, is determined. In addition, the thickness and composition for the individual quantum well layers is determined such that the peak in the optical gain will be achieved at the desired wavelength for each device. Array fabrication is commenced by depositing at least one layer having uniform composition and thickness on the III-V substrate. An oxide mask is formed on the at least one layer of uniform thickness. The oxide mask is a pattern of oxide pads that are used to control the MOCVD growth rate and the composition of III-V semiconductor material subsequently formed thereon. The oxide mask pattern is selected to provide a layer of III-V semiconductor material that meets the composition and dimension specifications for the devices in the array. After the desired pattern is determined, and the oxide pads are formed, a III-V semiconductor material is formed on the substrate by MOCVD. During the growth step, the quantum well layers of the desired thickness and composition are formed. The growth is continued until the desired &Dgr;L is obtained. MOCVD is then stopped and the oxide mask is removed. A layer of III-V semiconductor material having uniform composition and thickness is then deposited on the structure. This deposition step continues until sufficient material is deposited on the structure from which to form an array of devices having active regions with the desired Ln. A layer of material having uniform composition that will become the top mirror of the VCSEL devices is then deposited on the structure. The desired devices are then etched from the desired structure.
摘要:
A process for fabricating a waveguide with a desired tapered profile is disclosed. The waveguide has a first section with a first height and a second section with a second height. The first height is greater than the second height. The waveguide height tapers from the first height to the second height. The waveguide is a compound semiconductor material and is formed using selective area growth. In selective area growth, a dielectric mask is formed on a substrate. The dimensions of the dielectric mask are selected to provide a waveguide with the desired dimensions. The compound semiconductor material is deposited on the substrate using chemical vapor deposition. The dielectric mask affects the rate at which the compound material is deposited in areas of the substrate proximate to the mask. Therefore, the profile of the waveguide formed using the selected mask dimensions is modeled and compared with the desired profile. If modeled profile is not acceptably similar to the desired profile, the dimensions of the mask are modified. The profile of the waveguide formed using the modified mask dimensions is again modeled, and the modeled waveguide profile is compared with the desired waveguide profile. This process is repeated until the modeled profile is sufficiently similar to the desired profile. After the mask dimensions are selected, the mask is formed on the substrate, and the compound semiconductor waveguide is formed on the substrate using selective area growth.
摘要:
A micro-photoreflectance technique has been developed for performing non-destructive analysis of III-V optoelectronic devices. By using a significantly reduced spot size (for example, 10 micrometers), various compositional features of the device may be analyzed and the Franz-Keldysh oscillations appearing in the micro-photoreflectance wavelength spectra (such as those beyond the barrier/SCL wavelength in an EML structure) may be analyzed to provide information regarding the physical characteristics of the device, such as the electric field and p-i junction placement within an exemplary EML device structure.