公开(公告)号：US08603903B2

公开(公告)日：2013-12-10

申请号：US13443228

申请日：2012-04-10

申请人： Masahito Kanamura ,  Toshihide Kikkawa

发明人： Masahito Kanamura ,  Toshihide Kikkawa

IPC分类号： H01L21/28

CPC分类号： H01L29/41 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/7787

摘要： In an MIS-type GaN-FET, a base layer made of a conductive nitride including no oxygen, here, TaN, is provided on a surface layer as a nitride semiconductor layer to cover at least an area of a lower face of a gate insulation film made of Ta2O5 under a gate electrode.

摘要翻译： 在MIS型GaN-FET中，作为氮化物半导体层，在作为氮化物半导体层的表面层上设置由不含氧的导电性氮化物构成的基底层Ta N，以覆盖栅绝缘体的下表面的至少一部分 由Ta2O5制成的薄膜在栅电极下。

公开(公告)号：US20130075789A1

公开(公告)日：2013-03-28

申请号：US13606542

申请日：2012-09-07

申请人： Masahito KANAMURA ,  Toyoo Miyajima ,  Toshihiro Ohki

发明人： Masahito KANAMURA ,  Toyoo Miyajima ,  Toshihiro Ohki

IPC分类号： H01L29/778 ,  H01L21/336

CPC分类号： H01L29/42364 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787 ,  H01L2224/0603 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48472 ,  H01L2224/4903 ,  H03F1/3247

摘要： A semiconductor device, comprising: a first semiconductor layer disposed on a substrate; a second semiconductor layer disposed on the first semiconductor layer; a lower insulating film disposed on the second semiconductor layer; a p-type electroconductive oxide film disposed on the lower insulating film; an upper insulating film disposed on the oxide film; and a gate electrode disposed on the upper insulating film, wherein the lower insulating film under the gate electrode has a depressed portion.

摘要翻译： 一种半导体器件，包括：设置在基板上的第一半导体层; 设置在所述第一半导体层上的第二半导体层; 设置在所述第二半导体层上的下绝缘膜; 设置在下绝缘膜上的p型导电氧化物膜; 设置在氧化膜上的上绝缘膜; 以及设置在所述上​​绝缘膜上的栅电极，其中所述栅电极下的下绝缘膜具有凹陷部。

公开(公告)号：US08389351B2

公开(公告)日：2013-03-05

申请号：US13282812

申请日：2011-10-27

申请人： Toshihiro Ohki ,  Masahito Kanamura

发明人： Toshihiro Ohki ,  Masahito Kanamura

IPC分类号： H01L21/336

CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L2224/0603 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48472 ,  H01L2224/4903

摘要： A method for fabricating a semiconductor device is disclosed. A resist pattern is formed on a surface of a semiconductor layer in which a first layer and a second layer are sequentially formed on a substrate. A gate recess is formed by removing a part or the entire second layer in an opening area of the resist pattern. The resist pattern is removed. A dry etching residue attached to a bottom surface and lateral surfaces of the gate recess is removed after the resist pattern is removed. An insulating film is formed on the bottom surface, the lateral surfaces, and the semiconductor layer after the dry etching residue is removed. A gate electrode is formed via the insulating film on an area where the gate recess is formed. A source electrode and a drain electrode are formed on the semiconductor layer.

摘要翻译： 公开了一种制造半导体器件的方法。 在半导体层的表面上形成抗蚀剂图案，其中在衬底上依次形成第一层和第二层。 通过去除抗蚀剂图案的开口区域中的一部分或全部第二层来形成栅极凹部。 去除抗蚀剂图案。 在除去抗蚀剂图案之后，去除附着到底部表面和浇口凹槽的侧表面的干蚀刻残留物。 在去除干蚀刻残渣之后，在底表面，侧表面和半导体层上形成绝缘膜。 在形成栅极凹部的区域，经由绝缘膜形成栅电极。 源电极和漏电极形成在半导体层上。

公开(公告)号：US20110079771A1

公开(公告)日：2011-04-07

申请号：US12886822

申请日：2010-09-21

申请人： Masahito KANAMURA ,  Toshihide Kikkawa

发明人： Masahito KANAMURA ,  Toshihide Kikkawa

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/778 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

摘要： An intermediate layer composed of i-AlN is formed between a channel layer and an electron donor layer, a first opening is formed in an electron donor layer, at a position where a gate electrode will be formed later, while using an intermediate layer as an etching stopper, a second opening is formed in the intermediate layer so as to be positionally aligned with the first opening, by wet etching using a hot phosphoric acid solution, and a gate electrode is formed so that the lower portion thereof fill the first and second openings while placing a gate insulating film in between, and so that the head portion thereof projects above the cap structure.

摘要翻译： 在沟道层和电子给体层之间形成由i-AlN构成的中间层，在电子供体层中形成第一开口，在稍后将形成栅电极的位置，同时使用中间层作为 蚀刻停止器，通过使用热磷酸溶液的湿蚀刻，在中间层中形成第二开口以与第一开口位置对准，并且形成栅电极，使得其下部填充第一和第二 开口，同时将栅极绝缘膜放置在其间，并且使得其头部突出在盖结构的上方。

公开(公告)号：US20090194791A1

公开(公告)日：2009-08-06

申请号：US12412996

申请日：2009-03-27

申请人： Masahito Kanamura

发明人： Masahito Kanamura

IPC分类号： H01L29/205 ,  H01L21/20

CPC分类号： H01L29/66522 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7787

摘要： A compound semiconductor device including an electron transport layer that is formed on a substrate and includes a III-V nitride compound semiconductor, a gate insulating film that is positioned above the compound semiconductor layer, and a gate electrode that is positioned on the gate insulating film. The gate insulating film includes a first insulating film that includes oxygen, at least a single metal element selected from a metal bonding with the oxygen and forming a metal oxide having a dielectric constant no less than 10, and at least a single metal element selected from Si and Al.

摘要翻译： 一种化合物半导体器件，包括形成在衬底上并包括III-V族氮化物化合物半导体的电子传输层，位于化合物半导体层上方的栅极绝缘膜和位于栅极绝缘膜上的栅极电极 。 栅极绝缘膜包括：第一绝缘膜，其包括氧，至少一种金属元素，其选自与氧接合的金属并形成介电常数不小于10的金属氧化物，以及至少一种选自以下的金属元素： Si和Al。

公开(公告)号：US20070228415A1

公开(公告)日：2007-10-04

申请号：US11476205

申请日：2006-06-28

申请人： Masahito Kanamura ,  Masahiro Nishi

发明人： Masahito Kanamura ,  Masahiro Nishi

IPC分类号： H01L31/00 ,  H01L29/739

CPC分类号： H01L29/2003 ,  H01L21/28575 ,  H01L29/41725 ,  H01L29/452 ,  H01L29/7787

摘要： A semiconductor device is configured so as to comprise a substrate, an n-type semiconductor layer or an undoped semiconductor layer on the substrate, and an ohmic electrode on the n-type semiconductor layer or the undoped semiconductor layer, and the ohmic electrode is configured so as to comprise a tantalum layer formed on the n-type semiconductor layer or the undoped semiconductor layer, an aluminum layer formed on the tantalum layer, and a metal layer formed on the aluminum layer and made of any one material of tantalum, nickel, palladium, and molybdenum.

摘要翻译： 半导体器件被配置为在衬底上包括衬底，n型半导体层或未掺杂的半导体层，以及在n型半导体层或未掺杂的半导体层上的欧姆电极，并且构成欧姆电极 以形成在n型半导体层或未掺杂的半导体层上形成的钽层，在钽层上形成的铝层和形成在铝层上的由钽，镍， 钯和钼。

公开(公告)号：US08912571B2

公开(公告)日：2014-12-16

申请号：US13294654

申请日：2011-11-11

申请人： Masahito Kanamura ,  Toshihide Kikkawa ,  Kenji Imanishi

发明人： Masahito Kanamura ,  Toshihide Kikkawa ,  Kenji Imanishi

IPC分类号： H01L29/66 ,  H01L21/338 ,  H01L29/51 ,  H01L29/778 ,  H01L29/417

CPC分类号： H01L29/7787 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/47 ,  H01L29/513 ,  H01L29/66462

摘要： A compound semiconductor device includes: a compound semiconductor layer; a first film formed over the compound semiconductor layer, the first film being in a negatively charged state or a non-charged state at an interface with the compound semiconductor layer; a second film formed over the first film, the second film being in a positively charged state at an interface with the first film; and a gate electrode to be embedded in an opening formed in the second film.

摘要翻译： 化合物半导体器件包括：化合物半导体层; 形成在所述化合物半导体层上的第一膜，所述第一膜在与所述化合物半导体层的界面处于带负电状态或非带电状态; 形成在所述第一膜上的第二膜，所述第二膜在与所述第一膜的界面处于带电状态; 以及嵌入到形成在第二膜中的开口中的栅电极。

公开(公告)号：US20120149161A1

公开(公告)日：2012-06-14

申请号：US13282812

申请日：2011-10-27

申请人： Toshihiro Ohki ,  Masahito Kanamura

发明人： Toshihiro Ohki ,  Masahito Kanamura

IPC分类号： H01L21/335

CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L2224/0603 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48472 ,  H01L2224/4903

摘要： A method for fabricating a semiconductor device is disclosed. A resist pattern is formed on a surface of a semiconductor layer in which a first layer and a second layer are sequentially formed on a substrate. A gate recess is formed by removing a part or the entire second layer in an opening area of the resist pattern. The resist pattern is removed. A dry etching residue attached to a bottom surface and lateral surfaces of the gate recess is removed after the resist pattern is removed. An insulating film is formed on the bottom surface, the lateral surfaces, and the semiconductor layer after the dry etching residue is removed. A gate electrode is formed via the insulating film on an area where the gate recess is formed. A source electrode and a drain electrode are formed on the semiconductor layer.

摘要翻译： 公开了一种制造半导体器件的方法。 在半导体层的表面上形成抗蚀剂图案，其中在衬底上依次形成第一层和第二层。 通过去除抗蚀剂图案的开口区域中的一部分或全部第二层来形成栅极凹部。 去除抗蚀剂图案。 在除去抗蚀剂图案之后，去除附着到底部表面和浇口凹槽的侧表面的干蚀刻残留物。 在去除干蚀刻残渣之后，在底表面，侧表面和半导体层上形成绝缘膜。 在形成栅极凹部的区域，经由绝缘膜形成栅电极。 源电极和漏电极形成在半导体层上。

公开(公告)号：US20120138944A1

公开(公告)日：2012-06-07

申请号：US13294654

申请日：2011-11-11

申请人： Masahito KANAMURA ,  Toshihide KIKKAWA ,  Kenji IMANISHI

发明人： Masahito KANAMURA ,  Toshihide KIKKAWA ,  Kenji IMANISHI

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/7787 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/47 ,  H01L29/513 ,  H01L29/66462

摘要： A compound semiconductor device includes: a compound semiconductor layer; a first film formed over the compound semiconductor layer, the first film being in a negatively charged state or a non-charged state at an interface with the compound semiconductor layer; a second film formed over the first film, the second film being in a positively charged state at an interface with the first film; and a gate electrode to be embedded in an opening formed in the second film.

摘要翻译： 化合物半导体器件包括：化合物半导体层; 形成在所述化合物半导体层上的第一膜，所述第一膜在与所述化合物半导体层的界面处于带负电状态或非带电状态; 形成在所述第一膜上的第二膜，所述第二膜在与所述第一膜的界面处于带电状态; 以及嵌入到形成在第二膜中的开口中的栅电极。

公开(公告)号：US08173529B2

公开(公告)日：2012-05-08

申请号：US12805506

申请日：2010-08-03

申请人： Masahito Kanamura ,  Toshihide Kikkawa

发明人： Masahito Kanamura ,  Toshihide Kikkawa

IPC分类号： H01L21/28

CPC分类号： H01L29/41 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/7787

摘要： In an MIS-type GaN-FET, a base layer made of a conductive nitride including no oxygen, here, TaN, is provided on a surface layer as a nitride semiconductor layer to cover at least an area of a lower face of a gate insulation film made of Ta2O5 under a gate electrode.

摘要翻译： 在MIS型GaN-FET中，作为氮化物半导体层，在作为氮化物半导体层的表面层上设置由不含氧的导电性氮化物构成的基底层Ta N，以覆盖栅极绝缘体的下表面的至少一部分 由Ta2O5制成的薄膜在栅电极下。