公开(公告)号：US08554987B2

公开(公告)日：2013-10-08

申请号：US13061731

申请日：2010-05-14

申请人： Hirokazu So ,  Masayuki Toyama

发明人： Hirokazu So ,  Masayuki Toyama

IPC分类号： G06F12/02

CPC分类号： G06F12/0246

摘要： The nonvolatile memory device prevents data writing from temporarily slowing down significantly in the middle of writing data to a block when an access device writes all the data in the block in units of a smaller size than the block. The nonvolatile memory device comprises a memory controller including an interface unit configured to receive a first command that identifies a first write range for writing data, and a second command that identifies a second write range that is a part of the first write range and orders to write data to the second write range, an address management unit configured to determine, before data is written into a nonvolatile memory, a new block for writing data to the first write range based on the first command, and a read/write control unit configured to write data to the new block in response to the second command.

摘要翻译： 非易失性存储器件在访问设备以块大小的单位写入块中的所有数据时，防止数据写入中间向数据块写入数据时暂时减慢。 所述非易失性存储器件包括存储器控制器，所述存储器控制器包括被配置为接收标识用于写入数据的第一写入范围的第一命令的接口单元和识别作为所述第一写入范围的一部分的第二写入范围的第二命令， 将数据写入第二写入范围，地址管理单元，被配置为基于第一命令在数据被写入非易失性存储器之前确定用于将数据写入到第一写入范围的新块，并且配置为读/写控制单元 以响应于第二个命令将数据写入新块。

公开(公告)号：US08527691B2

公开(公告)日：2013-09-03

申请号：US12665064

申请日：2008-07-30

申请人： Toshiyuki Honda ,  Masayuki Toyama ,  Masahiro Nakanishi

发明人： Toshiyuki Honda ,  Masayuki Toyama ,  Masahiro Nakanishi

IPC分类号： G06F13/00

CPC分类号： G06F9/4403 ,  G06F12/0246 ,  G06F2212/7201

摘要： A nonvolatile storage device includes a controller and a nonvolatile memory. The controller has: a logical-physical address conversion part for converting a logical address designated by a host device into a physical address; and a boot code address conversion part for converting boot code address information designated by the host device into a physical address. After the power-on and before the logical-physical address conversion part becomes usable, a boot code is read from a part of region which can be accessed by designating a logical address from the host device by designating the boot code address information from the outside. Thus, it is possible to rapidly start the nonvolatile memory system after the power-on. In the state where the logical-physical address conversion part can be used, data-reading and data-writing are carried out by designating a logical address from the host device.

摘要翻译： 非易失性存储装置包括控制器和非易失性存储器。 控制器具有：逻辑 - 物理地址转换部分，用于将由主机设备指定的逻辑地址转换成物理地址; 以及引导代码地址转换部分，用于将由主机设备指定的引导代码地址信息转换为物理地址。 在上电之后并且在逻辑 - 物理地址转换部分变得可用之前，通过从外部指定引导代码地址信息从主机设备指定逻辑地址可以访问的区域的一部分读取引导代码 。 因此，可以在通电之后快速启动非易失性存储器系统。 在可以使用逻辑 - 物理地址转换部分的状态下，通过从主机设备指定逻辑地址来执行数据读取和数据写入。

公开(公告)号：US20110289176A1

公开(公告)日：2011-11-24

申请号：US13144300

申请日：2010-11-25

申请人： Masayuki Toyama

发明人： Masayuki Toyama

IPC分类号： G06F15/16

CPC分类号： H04L41/00 ,  H04L12/40006 ,  H04L12/40019 ,  H04L12/403 ,  H04L41/0843

摘要： A communication system including a master device and one or more slave devices enables parameters of the slave devices to be set in an efficient manner. A master device (2) transmits a parameter setting command as a broadcast command. A slave device (1) receives the parameter setting command, and compares the received parameter value with a parameter value stored in a parameter display unit, and transmits a parameter setting command to which the comparison result has been added. The master device (2) receives the parameter setting command transmitted from the slave device (1) and determines that the parameter setting has been completed.

摘要翻译： 包括主设备和一个或多个从设备的通信系统使得能够以有效的方式设置从设备的参数。 主设备（2）发送参数设置命令作为广播命令。 从设备（1）接收参数设置命令，并将接收到的参数值与参数显示单元中存储的参数值进行比较，并发送添加了比较结果的参数设置命令。 主设备（2）接收从从设备（1）发送的参数设置命令，并确定参数设置已经完成。

公开(公告)号：US20110276748A1

公开(公告)日：2011-11-10

申请号：US13144594

申请日：2010-12-01

申请人： Masayuki Toyama ,  Tadashi Ono ,  Shinichiro Nishioka

发明人： Masayuki Toyama ,  Tadashi Ono ,  Shinichiro Nishioka

IPC分类号： G06F12/02

CPC分类号： G06F9/4403

摘要： In a memory system including a host device and one or more nonvolatile memory devices, the host device reads, from a nonvolatile memory device connected in the system, a boot code used to operate a CPU of the host device before the CPU is activated. The boot code reading process is required to be performed with a simple method. A host device (2) transmits a first symbol including a synchronous code to a nonvolatile memory device (1). The nonvolatile memory device (1) receives the first symbol from the host device (2), and transmits a first symbol that is identical to the received first symbol to the host device (2), and then transmits a boot code to the host device (2). In this manner, the host device (2) reads a boot code from the nonvolatile memory device 1 with a simple method.

摘要翻译： 在包括主机设备和一个或多个非易失性存储设备的存储器系统中，主机设备从连接在系统中的非易失性存储设备中读取用于在CPU被激活之前操作主机设备的CPU的引导代码。 引导代码读取过程需要以简单的方法执行。 主机设备（2）将包括同步码的第一符号发送到非易失性存储设备（1）。 非易失性存储器件（1）从主机（2）接收第一符号，并将与接收到的第一符号相同的第一符号发送到主机（2），然后将引导代码发送到主机 （2）。 以这种方式，主机设备（2）以简单的方法从非易失性存储设备1读取引导代码。

公开(公告)号：US20110125928A1

公开(公告)日：2011-05-26

申请号：US13014875

申请日：2011-01-27

申请人： Masayuki TOYAMA ,  Takuji MAEDA ,  Tomoaki IZUMI ,  Shouichi TSUJITA ,  Masahiro NAKANISHI ,  Shinji INOUE

发明人： Masayuki TOYAMA ,  Takuji MAEDA ,  Tomoaki IZUMI ,  Shouichi TSUJITA ,  Masahiro NAKANISHI ,  Shinji INOUE

IPC分类号： G06F3/01

CPC分类号： G06F3/0659 ,  G06F3/0619 ,  G06F3/0679

摘要： A host device is connected to a storage device via a bus and reads and writes data in the storage device. The host device includes a command transmitter that sequentially transmits a command in a command sequence, which includes a set of commands which do not change data stored in the storage device, and a response receptor that accepts a response from the storage device for each command transmission from the command transmitter and determines whether or not an error exists. An acceptable/unacceptable access determiner provided in the host device enables access to the storage device when a normal response is identified by the response receptor and otherwise determines that access to the storage device is unacceptable. The normal response is when the responses received from the storage device for the transmissions of all commands in the command sequence do not include an error.

摘要翻译： 主机通过总线连接到存储设备，并在存储设备中读取和写入数据。 主机装置包括命令发送器，其顺序地发送命令序列中的命令，该命令序列包括不改变存储在存储装置中的数据的一组命令，以及响应接收器，用于接收来自存储装置的每个命令传输的响应 从命令发送器确定是否存在错误。 在主机设备中提供的可接受/不能接受的访问确定器使得能够在响应受体识别出正常响应时访问存储设备，并且另外确定对存储设备的访问是不可接受的。 正常响应是当从存储设备接收的用于命令序列中的所有命令的传输的响应不包括错误。

公开(公告)号：US07940086B2

公开(公告)日：2011-05-10

申请号：US12847161

申请日：2010-07-30

申请人： Hiroshi Suenaga ,  Osamu Shibata ,  Yoshiyuki Saito ,  Toru Iwata ,  Masayuki Toyama ,  Kyoko Hirata

发明人： Hiroshi Suenaga ,  Osamu Shibata ,  Yoshiyuki Saito ,  Toru Iwata ,  Masayuki Toyama ,  Kyoko Hirata

IPC分类号： H03K19/094

CPC分类号： H04L25/028 ,  H04L25/0272

摘要： An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.

摘要翻译： 本发明的目的是实现在两个传输系统之间切换的接口电路中的输出级驱动器的面积的减小。 接口电路具有两个驱动电路和驱动控制电路，该电路可以在作为电压驱动系统和电流驱动系统的两个驱动系统之间切换。 两个驱动电路通过驱动控制电路连接到电源电位。 通过选择电路输入输入信号的两个输入信号和反相逻辑信号。 根据输入到驱动控制电路的控制信号，接口电路在电压驱动型单端传输系统和电流驱动型差动传输系统之间切换。

公开(公告)号：US07900007B2

公开(公告)日：2011-03-01

申请号：US11571592

申请日：2005-06-28

申请人： Masayuki Toyama ,  Takuji Maeda ,  Tomoaki Izumi ,  Shouichi Tsujita ,  Masahiro Nakanishi ,  Shinji Inoue

发明人： Masayuki Toyama ,  Takuji Maeda ,  Tomoaki Izumi ,  Shouichi Tsujita ,  Masahiro Nakanishi ,  Shinji Inoue

IPC分类号： G06F13/14

CPC分类号： G06F3/0659 ,  G06F3/0619 ,  G06F3/0679

摘要： A host device transmits a command from a command transmission unit (101a) along a predetermined command sequence. A storage device (2) receives the command in a command reception unit (202a). An access determination unit (202c) determines the sequence of the command transmitted from the host device (1) and determines that reception of the access to the host device (1) is enabled only when the sequence is identical with a predetermined sequence. Thus, with simple control, it is possible to prevent data destruction by a host device of an old version.

摘要翻译： 主机设备沿着预定的命令序列从命令发送单元（101a）发送命令。 存储装置（2）在命令接收部（202a）中接收命令。 访问确定单元（202c）确定从主机设备（1）发送的命令的顺序，并且确定只有当序列与预定序列相同时，对主机设备（1）的访问的接收才被使能。 因此，通过简单的控制，可以防止主机装置破坏老版本的数据。

公开(公告)号：US07702846B2

公开(公告)日：2010-04-20

申请号：US11908715

申请日：2006-03-09

申请人： Masahiro Nakanishi ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Kazuaki Tamura ,  Kiminori Matsuno ,  Yutaka Nakamura ,  Masayuki Toyama ,  Yasushi Goho ,  Syunichi Iwanari ,  Yoshihisa Kato ,  Manabu Inoue

发明人： Masahiro Nakanishi ,  Tomoaki Izumi ,  Tetsushi Kasahara ,  Kazuaki Tamura ,  Kiminori Matsuno ,  Yutaka Nakamura ,  Masayuki Toyama ,  Yasushi Goho ,  Syunichi Iwanari ,  Yoshihisa Kato ,  Manabu Inoue

IPC分类号： G06F12/12

CPC分类号： G06F3/0656 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0643 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/7203

摘要： A nonvolatile storage device is provided with a nonvolatile main storage memory whose erase size is larger than a cluster size, and a buffer, i.e. a nonvolatile auxiliary storage memory. At the time of writing data in the memory, the data is temporarily stored in the buffer, then, a plurality of data in the buffer are collectively taken out to be stored in the main storage memory. Data in an original block is saved in a write block in the main storage memory. Thus, the data can be written in the main storage memory at a high speed.

摘要翻译： 非易失性存储装置具有擦除大小大于簇大小的非易失性主存储存储器和缓冲器，即非易失性辅助存储存储器。 在将数据写入存储器时，将数据临时存储在缓冲器中，然后将缓冲器中的多个数据共同取出以存储在主存储器中。 原始块中的数据保存在主存储器中的写入块中。 因此，可以高速地将数据写入主存储存储器。

公开(公告)号：US07516344B2

公开(公告)日：2009-04-07

申请号：US11338770

申请日：2006-01-25

申请人： Yoshihisa Kato ,  Yasushi Gohou ,  Masahiro Nakanishi ,  Masayuki Toyama ,  Shunichi Iwanari

发明人： Yoshihisa Kato ,  Yasushi Gohou ,  Masahiro Nakanishi ,  Masayuki Toyama ,  Shunichi Iwanari

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F13/00 ,  G06F13/28 ,  G11C16/04 ,  G11C15/00

CPC分类号： G06F1/3225 ,  G06F1/206 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172

摘要： A memory system of the present invention includes a memory device having a nonvolatile memory and an access device which accesses the memory device. The memory device has a detection unit to detect a temperature of the memory device, a determination unit to determine an operating condition in accordance with the detected temperature and a notification unit to notify the access device of the determined operating condition. The access device has an interface unit to connect to the memory device and a controlling unit to control the interface unit in accordance with the notified operating condition from the memory device.

摘要翻译： 本发明的存储器系统包括具有非易失性存储器的存储器件和访问存储器件的存取器件。 存储装置具有检测单元，用于检测存储装置的温度，确定单元，以根据检测到的温度确定运行状况;以及通知单元，用于向所述存取装置通知所确定的运行状况。 接入设备具有连接到存储设备的接口单元和控制单元，以根据来自存储设备的所通知的操作条件来控制接口单元。

公开(公告)号：US20080109627A1

公开(公告)日：2008-05-08

申请号：US11718965

申请日：2005-11-08

申请人： Masayuki Toyama ,  Tomoaki Izumi ,  Kazuaki Tamura ,  Kiminori Matsuno ,  Manabu Inoue ,  Masahiro Nakanishi

发明人： Masayuki Toyama ,  Tomoaki Izumi ,  Kazuaki Tamura ,  Kiminori Matsuno ,  Manabu Inoue ,  Masahiro Nakanishi

IPC分类号： G06F12/00

CPC分类号： G06F13/1647 ,  G06F12/0607

摘要： The present invention provides a nonvolatile memory device that can be used in combination with a plurality of types of memory controllers that are different in number of banks to be simultaneously accessed, the nonvolatile memory device being also capable of achieving high-speed access.The nonvolatile memory device of the present invention includes: a memory area divided into a plurality of banks from/to which data can be read/written independently; and data registers for storing data that has been read from the memory area or that is to be written to the memory area, the data registers being at least equal in number to the banks, and connections between the banks and the data registers are changed in accordance with the number of banks that are to be simultaneously accessed.

摘要翻译： 本发明提供一种非易失性存储器件，其可以与要同时存取的存储体数不同的多种存储器控制器组合使用，非易失性存储器件也能够实现高速存取。 本发明的非易失性存储装置包括：分割成可独立读/写数据的多个存储体的存储区域; 以及数据寄存器，用于存储已经从存储器区域读取或要写入存储区域的数据，数据寄存器的数量至少等于存储区，并且存储体和数据寄存器之间的连接被改变为 按照同时访问的银行数量。