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1.发明授权公开(公告)号：US08863046B2
公开(公告)日：2014-10-14
申请号：US12101449
申请日：2008-04-11
CPC分类号： H05K1/024 , H05K3/4652 , H05K2201/0195 , H05K2201/0715 , H05K2201/09236 , H05K2201/09881 , Y10T156/10 , Y10T428/24628
摘要： Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer electronic structure and a method of manufacture is presented.
摘要翻译： 阻抗控制以及电子封装中电气和机械特性的均匀性越来越重要，因为芯片和总线速度的增加和制造过程的演变。 当前的现有技术设计和制造工艺本身将物理电介质厚度变化引入PCB横截面。 接地参考平面与信号层之间的这些厚度变化引起了不需要的特性阻抗变化和厚度和表面拓扑结构中不期望的机械变化。 因此，提出了一种多层电子结构和制造方法。
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2.发明申请公开(公告)号：US20090258194A1
公开(公告)日：2009-10-15
申请号：US12101449
申请日：2008-04-11
CPC分类号： H05K1/024 , H05K3/4652 , H05K2201/0195 , H05K2201/0715 , H05K2201/09236 , H05K2201/09881 , Y10T156/10 , Y10T428/24628
摘要： Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer electronic structure and a method of manufacture is presented.
摘要翻译： 阻抗控制以及电子封装中电气和机械特性的均匀性越来越重要，因为芯片和总线速度的增加和制造过程的演变。 当前的现有技术设计和制造工艺本身将物理电介质厚度变化引入PCB横截面。 接地参考平面与信号层之间的这些厚度变化引起了不需要的特性阻抗变化和厚度和表面拓扑结构中不期望的机械变化。 因此，提出了一种多层电子结构和制造方法。
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3.发明申请公开(公告)号：US20090255715A1
公开(公告)日：2009-10-15
申请号：US12101441
申请日：2008-04-11
CPC分类号： H05K1/024 , H01P11/003 , H05K1/0298 , H05K2201/0191 , H05K2201/0715 , H05K2201/09881 , H05K2203/063
摘要： Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into multilayer cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer structure and a method of manufacture are presented.
摘要翻译： 阻抗控制以及电子封装中电气和机械特性的均匀性越来越重要，因为芯片和总线速度的增加和制造过程的演变。 现有技术的设计和制造工艺现在将物理电介质厚度变化引入到多层横截面中。 接地参考平面与信号层之间的这些厚度变化引起了不需要的特性阻抗变化和厚度和表面拓扑结构中不期望的机械变化。 因此，提出了多层结构和制造方法。
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公开(公告)号：US20090211792A1
公开(公告)日：2009-08-27
申请号：US12035683
申请日：2008-02-22
CPC分类号： H05K1/024 , H05K1/0393 , H05K3/386 , H05K3/4626 , H05K3/4635 , H05K3/4688 , H05K2201/015 , H05K2201/0191 , H05K2201/0715 , Y10T29/49126 , Y10T29/49128 , Y10T29/49163
摘要： A flexible printed circuit assembly with a fluorocarbon dielectric layer and an adhesive layer with reduced thickness. The flexible printed circuit assembly includes a first dielectric layer and a signal trace disposed on the first dielectric layer. An adhesive layer with a thickness smaller than a height of the signal trace is disposed on the first dielectric layer, so that only a portion of a side surface of the signal trace is covered. A second dielectric layer made of fluorocarbon is disposed on the adhesive layer, covering a remaining portion of the side surface of the signal trace and a top surface of the signal trace.
摘要翻译： 一种柔性印刷电路组件，具有碳氟介电层和厚度减小的粘合剂层。 柔性印刷电路组件包括第一介电层和布置在第一介电层上的信号迹线。 厚度小于信号迹线的高度的粘合剂层设置在第一介电层上，使得仅覆盖信号迹线的侧表面的一部分。 由氟碳制成的第二电介质层设置在粘合剂层上，覆盖信号迹线的侧表面的剩余部分和信号迹线的顶表面。
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公开(公告)号：US07086869B1
公开(公告)日：2006-08-08
申请号：US11038708
申请日：2005-01-20
申请人： John Richard Dangler , Matthew Stephen Doyle , Thomas Donald Kidd , Bradley Lewis Martin , Kevin J. Przybylski , Jason Thomas Stoll
发明人： John Richard Dangler , Matthew Stephen Doyle , Thomas Donald Kidd , Bradley Lewis Martin , Kevin J. Przybylski , Jason Thomas Stoll
IPC分类号： H01R12/00
CPC分类号： H05K1/0218 , H01B7/0861 , H05K1/0393 , H05K3/4611 , H05K3/4635 , H05K2201/0715 , H05K2201/09318 , H05K2201/09618
摘要： In a flat flex cable, signal lines are surrounded by logic ground planes above and below which are viaed together left and right. The ground planes coupled with the flex cable dielectric determine characteristic the impedance and attenuation of the cable and provide differential signal EMI shielding. All signal layers and logic ground planes are enclosed within the two outermost shield layers which are viaed together left and right and around the connectors to enclose both signal layers and logic ground planes to provide common mode EMI shielding.
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6.发明授权公开(公告)号：US08549444B2
公开(公告)日：2013-10-01
申请号：US12101441
申请日：2008-04-11
CPC分类号： H05K1/024 , H01P11/003 , H05K1/0298 , H05K2201/0191 , H05K2201/0715 , H05K2201/09881 , H05K2203/063
摘要： Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into multilayer cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer structure and a method of manufacture are presented.
摘要翻译： 阻抗控制以及电子封装中电气和机械特性的均匀性越来越重要，因为芯片和总线速度的增加和制造过程的演变。 现有技术的设计和制造工艺现在将物理电介质厚度变化引入到多层横截面中。 接地参考平面与信号层之间的这些厚度变化引起了不需要的特性阻抗变化和厚度和表面拓扑结构中不期望的机械变化。 因此，提出了多层结构和制造方法。
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7.发明授权公开(公告)号：US08251749B2
公开(公告)日：2012-08-28
申请号：US12948049
申请日：2010-11-17
申请人： John Richard Dangler , Matthew Stephen Doyle , Thomas Donald Kidd , Joseph Kuczynski , Kevin Albert Splittstoesser , Timothy Jerome Tofil
发明人： John Richard Dangler , Matthew Stephen Doyle , Thomas Donald Kidd , Joseph Kuczynski , Kevin Albert Splittstoesser , Timothy Jerome Tofil
IPC分类号： H01R13/66
CPC分类号： H01R13/6477 , B29C45/0013 , B29C45/16 , B29K2995/0005 , H01R13/6587 , H01R43/24 , Y10T29/49204
摘要： A method and connector housing are provided for implementing an impedance gradient connector for board-to-board applications. The impedance gradient connector housing includes a plurality of impedance zones with a first impedance zone including a first mating face with a first Printed Circuit Board (PCB) and with a second impedance zone including a second mating face with a second PCB. Each of the respective predefined impedance zones including the first mating face and the second mating face include a selected impedance to minimize impedance mismatch with associated PCBs.
摘要翻译： 提供了一种用于实现用于板对板应用的阻抗梯度连接器的方法和连接器壳体。 阻抗梯度连接器壳体包括具有第一阻抗区域的多个阻抗区域，第一阻抗区域包括具有第一印刷电路板（PCB）的第一配合面，以及包括具有第二PCB的第二配合面的第二阻抗区域。 包括第一配对面和第二配对面的各自的预定阻抗区域中的每一个包括选择的阻抗以使与相关联的PCB的阻抗失配最小化。
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8.发明申请公开(公告)号：US20120122342A1
公开(公告)日：2012-05-17
申请号：US12948049
申请日：2010-11-17
申请人： John Richard Dangler , Matthew Stephen Doyle , Thomas Donald Kidd , Joseph Kuczynski , Kevin Albert Splittstoesser , Timothy Jerome Tofil
发明人： John Richard Dangler , Matthew Stephen Doyle , Thomas Donald Kidd , Joseph Kuczynski , Kevin Albert Splittstoesser , Timothy Jerome Tofil
CPC分类号： H01R13/6477 , B29C45/0013 , B29C45/16 , B29K2995/0005 , H01R13/6587 , H01R43/24 , Y10T29/49204
摘要： A method and connector housing are provided for implementing an impedance gradient connector for board-to-board applications. The impedance gradient connector housing includes a plurality of impedance zones with a first impedance zone including a first mating face with a first Printed Circuit Board (PCB) and with a second impedance zone including a second mating face with a second PCB. Each of the respective predefined impedance zones including the first mating face and the second mating face include a selected impedance to minimize impedance mismatch with associated PCBs.
摘要翻译： 提供了一种用于实现用于板对板应用的阻抗梯度连接器的方法和连接器壳体。 阻抗梯度连接器壳体包括具有第一阻抗区域的多个阻抗区域，第一阻抗区域包括具有第一印刷电路板（PCB）的第一配合面，以及包括具有第二PCB的第二配合面的第二阻抗区域。 包括第一配对面和第二配对面的各自的预定阻抗区域中的每一个包括选择的阻抗以使与相关联的PCB的阻抗失配最小化。
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公开(公告)号：US08015701B2
公开(公告)日：2011-09-13
申请号：US12035683
申请日：2008-02-22
IPC分类号： H05K3/20
CPC分类号： H05K1/024 , H05K1/0393 , H05K3/386 , H05K3/4626 , H05K3/4635 , H05K3/4688 , H05K2201/015 , H05K2201/0191 , H05K2201/0715 , Y10T29/49126 , Y10T29/49128 , Y10T29/49163
摘要： A flexible printed circuit assembly with a fluorocarbon dielectric layer and an adhesive layer with reduced thickness. The flexible printed circuit assembly includes a first dielectric layer and a signal trace disposed on the first dielectric layer. An adhesive layer with a thickness smaller than a height of the signal trace is disposed on the first dielectric layer, so that only a portion of a side surface of the signal trace is covered. A second dielectric layer made of fluorocarbon is disposed on the adhesive layer, covering a remaining portion of the side surface of the signal trace and a top surface of the signal trace.
摘要翻译： 一种柔性印刷电路组件，具有碳氟介电层和厚度减小的粘合剂层。 柔性印刷电路组件包括第一介电层和布置在第一介电层上的信号迹线。 厚度小于信号迹线的高度的粘合剂层设置在第一介电层上，使得仅覆盖信号迹线的侧表面的一部分。 由氟碳制成的第二电介质层设置在粘合剂层上，覆盖信号迹线的侧表面的剩余部分和信号迹线的顶表面。
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10.发明授权公开(公告)号：US07921403B2
公开(公告)日：2011-04-05
申请号：US12101455
申请日：2008-04-11
IPC分类号： G06F17/50 , H03K17/693 , H05K1/00 , H05K1/09
CPC分类号： H05K1/024 , G06F17/5018 , H01P11/003 , H05K1/0298 , H05K3/0005 , H05K2201/0191 , H05K2201/0715 , H05K2201/09881 , H05K2203/063
摘要： Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a process of generating equalization data and a design structure for multilayer electronic structures is presented.
摘要翻译： 阻抗控制以及电子封装中电气和机械特性的均匀性越来越重要，因为芯片和总线速度的增加和制造过程的演变。 当前的现有技术设计和制造工艺本身将物理电介质厚度变化引入PCB横截面。 接地参考平面与信号层之间的这些厚度变化引起了不需要的特性阻抗变化和厚度和表面拓扑结构中不期望的机械变化。 因此，提出了产生均衡数据的过程和用于多层电子结构的设计结构。
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