公开(公告)号：US20050164479A1

公开(公告)日：2005-07-28

申请号：US10766596

申请日：2004-01-27

申请人： Baw-Ching Perng ,  Yuan-Hung Chiu ,  Mei-Hui Sung ,  Peng-Fu Hsu

发明人： Baw-Ching Perng ,  Yuan-Hung Chiu ,  Mei-Hui Sung ,  Peng-Fu Hsu

IPC分类号： H01L21/20 ,  H01L21/28 ,  H01L21/311 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/51

CPC分类号： H01L21/3065 ,  H01L21/28194 ,  H01L21/31122 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66583

摘要： A method is described for selectively etching a high k dielectric layer that is preferably a hafnium or zirconium oxide, silicate, nitride, or oxynitride with a selectivity of greater than 2:1 relative to silicon oxide, polysilicon, or silicon. The plasma etch chemistry is comprised of one or more halogen containing gases such as CF4, CHF3, CH2F2, CH3F, C4F8, C4F6, C5F6, BCl3, Br2, HF, HCl, HBr, HI, and NF3 and leaves no etch residues. An inert gas or an inert gas and oxidant gas may be added to the halogen containing gas. In one embodiment, a high k gate dielectric layer is removed on portions of an active area in a MOS transistor. Alternatively, the high k dielectric layer is used in a capacitor between two conducting layers and is selectively removed from portions of an ILD layer.

摘要翻译： 描述了一种相对于氧化硅，多晶硅或硅选择性地蚀刻优选为铪或氧化锆，硅酸盐，氮化物或氮氧化物的高k电介质层的方法，其选择性大于2:1。 等离子体蚀刻化学性质由一种或多种含卤素气体组成，例如CF 4，CH 3 3，CH 2 F 2， CH 3，CH 3，CH 3，CH 3，CH 3，CH 3，CH 3， C 5，C 5，F 5，BCl 3，Br 2，HF，HCl，HBr，HI， 和NF 3，并且不留下蚀刻残留物。 可以向含卤素的气体中加入惰性气体或惰性气体和氧化剂气体。 在一个实施例中，在MOS晶体管的有源区域的部分上去除高k栅极电介质层。 或者，高k电介质层用于两个导电层之间的电容器中，并且从ILD层的部分选择性地去除。

公开(公告)号：US06440838B1

公开(公告)日：2002-08-27

申请号：US09996458

申请日：2001-11-20

申请人： Ming-Huei Lui ,  Mei-Hui Sung

发明人： Ming-Huei Lui ,  Mei-Hui Sung

IPC分类号： H01L214763

CPC分类号： H01L21/76832 ,  H01L21/7681 ,  H01L21/76835

摘要： Within a dual damascene method for forming a dual damascene aperture within a microelectronic fabrication there is employed a bottom etch stop layer formed of a first material and an intermediate etch stop layer formed as a laminate of a second material having formed thereupon a third material. Within the method, the second material serves as an etch stop for the first material and the third material, which may be identical materials. Within the method, there may be etched completely through the bottom etch stop layer to reach a contact region formed there beneath while not etching completely through the intermediate etch stop layer to reach a first dielectric layer formed there beneath.

摘要翻译： 在用于在微电子制造中形成双镶嵌孔的双镶嵌方法中，采用由第一材料形成的底部蚀刻停止层和形成为具有第三材料的第二材料的叠层的中间蚀刻停止层。 在该方法中，第二材料用作用于第一材料和第三材料的蚀刻停止件，其可以是相同的材料。 在该方法中，可以通过底部蚀刻停止层完全蚀刻到达其下形成的接触区域，而不通过中间蚀刻停止层完全蚀刻，以到达其下方形成的第一介电层。

公开(公告)号：US06689695B1

公开(公告)日：2004-02-10

申请号：US10184790

申请日：2002-06-28

申请人： Meng-Huei Lui ,  Mei-Hui Sung

发明人： Meng-Huei Lui ,  Mei-Hui Sung

IPC分类号： H01L21311

CPC分类号： H01L21/76808 ,  H01L21/0271 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/31144

摘要： A method is disclosed for forming dual damascene structures with a multi-purpose composite mask. The composite mask serves not only to prevent via poisoning, but also to improve the lithographic characteristics of forming a dual damascene structure. This is accomplished by using a mask comprising silicon-based as well as polymeric dielectric layers. Thus, one of the components of the composite mask, namely, the polymeric dielectric, makes it possible to protect the via openings by conformally covering the sidewalls of the via and, at the same time, by bringing controllability to the height of the protective dielectric in the via opening. In addition, because the polymeric dielectric also serves as the main plasma resisting layer during the trench etch, the required photoresist is much thinner; therefore, the lithography process window can be extended beneficially.

摘要翻译： 公开了一种用多用途复合掩模形成双镶嵌结构的方法。 复合掩模不仅用于防止通过中毒，而且还改善了形成双镶嵌结构的平版印刷特性。 这通过使用包含硅基和聚合物电介质层的掩模来实现。 因此，复合掩模的一个部件，即聚合物电介质，可以通过保形地覆盖通孔的侧壁来保护通孔开口，同时通过使保护电介质的高度可控制 在通孔开口。 此外，由于聚合物电介质还在沟槽蚀刻期间用作主等离子体抗蚀层，因此所需的光致抗蚀剂要薄得多; 因此，光刻工艺窗口可以有利地扩展。

公开(公告)号：US06582974B2

公开(公告)日：2003-06-24

申请号：US09990813

申请日：2001-11-15

申请人： Lawrence MH Lui ,  Mei-Hui Sung

发明人： Lawrence MH Lui ,  Mei-Hui Sung

IPC分类号： H01L214763

CPC分类号： H01L21/76829 ,  H01L21/76807

摘要： Within a dual damascene method for forming a dual damascene aperture within a microelectronic fabrication there is employed an etch stop layer interposed between a first dielectric layer and second dielectric layer within a non active product region of a substrate, but not within an active product region of the substrate. Within the dual damascene method, an endpoint for forming a trench within a dual damascene aperture within the active product region is sensed by reaching the etch stop layer when forming a dummy trench within the non active product region.

摘要翻译： 在用于在微电子制造中形成双镶嵌孔的双镶嵌方法中，采用了介于基材的非活性产物区域内的第一介电层和第二介电层之间的蚀刻停止层，但不在位于 底物。 在双镶嵌方法中，当在非活性产品区域内形成虚拟沟槽时，通过到达蚀刻停止层来感测用于在活性产品区域内的双镶嵌孔内形成沟槽的端点。

公开(公告)号：US06647994B1

公开(公告)日：2003-11-18

申请号：US10038709

申请日：2002-01-02

申请人： Ming-Huei Lui ,  Mei-Hui Sung

发明人： Ming-Huei Lui ,  Mei-Hui Sung

IPC分类号： H01L21302

CPC分类号： H01L21/31138 ,  G03F7/427

摘要： An improved and new process for photoresist stripping for use during fabrication of semiconductor integrated circuits, which use porous low-k dielectric materials, such as OSG or HSQ, as the interlevel and intra-level insulating layers, has been developed. Photoresist stripping in microwave or rf generated plasmas in gaseous mixtures of NH3 and CO takes place without attack or damage to underlying layers of OSG or HSQ. Optimum results are obtained when the ratio of CO to NH3 is between about 0.8 and 1.2.

摘要翻译： 已经开发了一种用于光致抗蚀剂剥离的改进的新方法，其用于制造半导体集成电路期间，其使用诸如OSG或HSQ的多孔低k电介质材料作为层间和层内绝缘层。 在NH3和CO的气体混合物中的微波或rf产生的等离子体中的光致抗蚀剂剥离不会对OSG或HSQ的下层产生攻击或损坏。 当CO与NH 3的比例在约0.8和1.2之间时，获得最佳结果。

公开(公告)号：US06380090B1

公开(公告)日：2002-04-30

申请号：US09174143

申请日：1998-10-16

申请人： Mei-Hui Sung ,  Shih-Kuan Tai

发明人： Mei-Hui Sung ,  Shih-Kuan Tai

IPC分类号： H01L213065

CPC分类号： H01L21/67126 ,  H01L21/67017 ,  H01L21/67775

摘要： A method and a structure for protecting a work piece in a semiconductor manufacturing process includes a cassette for mounting therein the work pieces and a sheet piece for shielding the work pieces; and a working platform for mounting thereon said cassette. Furthermore, there is a lid covering the working platform in order to prevent a contaminant from entering the cassette during the semiconductor manufacturing process so that the gate oxide loss of every wafer in the cassette will be reduced.

摘要翻译： 用于在半导体制造工艺中保护工件的方法和结构包括用于安装工件的盒和用于遮蔽工件的片件; 以及用于在其上安装所述盒的工作平台。 此外，为了防止污染物在半导体制造过程中进入盒子，盖子覆盖工作平台，使得盒子中的每个晶片的栅极氧化物损失减小。

公开(公告)号：US6024802A

公开(公告)日：2000-02-15

申请号：US124879

申请日：1998-07-30

申请人： Mei-Hui Sung ,  Shih-Kuan Tai

发明人： Mei-Hui Sung ,  Shih-Kuan Tai

IPC分类号： H01L21/306 ,  H01L21/318 ,  B08B6/00 ,  B08B1/02 ,  B08B3/00 ,  B08B7/04

CPC分类号： H01L21/02049 ,  H01L21/3185 ,  Y10S134/902

摘要： A vapor processing method for reducing oxide material depletion includes an early step of placing a polymer-coated substrate inside a vapor process chamber (VPC), a pre-processing step of passing an inert gas into the VPC for a definite period followed by an idling period, a clearing step of passing a reactive gas carried by an inert carrier into the VPC for clearing away previously deposited polymer on the substrate, and a post-processing step of passing an inert gas into the VPC to purge any unreacted reactive gases. Thereafter, the substrate is transferred to a dry task chamber (DTC) for cleaning, wherein the cleaning includes removing any residual gases on the wafer surface. Time required for cleaning the wafer in the DTC is smaller than the total time required for pre-processing, polymer clearing and post-processing.

摘要翻译： 用于减少氧化物材料消耗的蒸气处理方法包括将聚合物涂覆的基材放置在蒸气处理室（VPC）内的早期步骤，将惰性气体进入VPC一段时间后进行空转的预处理步骤 期间，将由惰性载体携带的反应气体通入VPC中以清除基板上预先沉积的聚合物的清除步骤，以及将惰性气体进入VPC以清除任何未反应的反应气体的后处理步骤。 此后，将衬底转移到干燥任务室（DTC）以进行清洁，其中清洁包括去除晶片表面上的任何残留气体。 在DTC中清洁晶片所需的时间小于预处理，聚合物清除和后处理所需的总时间。

公开(公告)号：US07012027B2

公开(公告)日：2006-03-14

申请号：US10766596

申请日：2004-01-27

申请人： Baw-Ching Perng ,  Yuan-Hung Chiu ,  Mei-Hui Sung ,  Peng-Fu Hsu

发明人： Baw-Ching Perng ,  Yuan-Hung Chiu ,  Mei-Hui Sung ,  Peng-Fu Hsu

IPC分类号： H01L21/31

CPC分类号： H01L21/3065 ,  H01L21/28194 ,  H01L21/31122 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66583

摘要： A method is described for selectively etching a high k dielectric layer that is preferably a hafnium or zirconium oxide, silicate, nitride, or oxynitride with a selectivity of greater than 2:1 relative to silicon oxide, polysilicon, or silicon. The plasma etch chemistry is comprised of one or more halogen containing gases such as CF4, CHF3, CH2F2, CH3F, C4F8, C4F6, C5F6, BCl3, Br2, HF, HCl, HBr, HI, and NF3 and leaves no etch residues. An inert gas or an inert gas and oxidant gas may be added to the halogen containing gas. In one embodiment, a high k gate dielectric layer is removed on portions of an active area in a MOS transistor. Alternatively, the high k dielectric layer is used in a capacitor between two conducting layers and is selectively removed from portions of an ILD layer.

摘要翻译： 描述了一种相对于氧化硅，多晶硅或硅选择性地蚀刻优选为铪或氧化锆，硅酸盐，氮化物或氮氧化物的高k电介质层的方法，其选择性大于2:1。 等离子体蚀刻化学性质由一种或多种含卤素气体组成，例如CF 4，CH 3 3，CH 2 F 2， CH 3，CH 3，CH 3，CH 3，CH 3，CH 3，CH 3， C 5，C 5，F 5，BCl 3，Br 2，HF，HCl，HBr，HI， 和NF 3，并且不留下蚀刻残留物。 可以向含卤素的气体中加入惰性气体或惰性气体和氧化剂气体。 在一个实施例中，在MOS晶体管的有源区域的部分上去除高k栅极电介质层。 或者，高k电介质层用于两个导电层之间的电容器中，并且从ILD层的部分选择性地去除。