公开(公告)号：US07790556B2

公开(公告)日：2010-09-07

申请号：US11148721

申请日：2005-06-09

申请人： Christophe F. Pomarede ,  Michael E. Givens ,  Eric J. Shero ,  Michael A. Todd

发明人： Christophe F. Pomarede ,  Michael E. Givens ,  Eric J. Shero ,  Michael A. Todd

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/763

CPC分类号： H01L21/28194 ,  B82Y10/00 ,  C23C16/0272 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/28035 ,  H01L21/28044 ,  H01L21/28525 ,  H01L21/28556 ,  H01L29/4925 ,  H01L29/517 ,  H01L31/1804 ,  H01L31/182 ,  H01L31/202 ,  Y02E10/546 ,  Y02E10/547 ,  Y02P70/521

摘要： Methods are provided herein for forming electrode layers over high dielectric constant (“high k”) materials. In the illustrated embodiments, a high k gate dielectric, such as zirconium oxide, is protected from reduction during a subsequent deposition of silicon-containing gate electrode. In particular, a seed deposition phase includes conditions designed for minimizing hydrogen reduction of the gate dielectric, including low hydrogen content, low temperatures and/or low partial pressures of the silicon source gas. Conditions are preferably changed for higher deposition rates and deposition continues in a bulk phase. Desirably, though, hydrogen diffusion is still minimized by controlling the above-noted parameters. In one embodiment, high k dielectric reduction is minimized through omission of a hydrogen carrier gas. In another embodiment, higher order silanes, aid in reducing hydrogen content for a given deposition rate.

摘要翻译： 本文提供了用于在高介电常数（“高k”）材料上形成电极层的方法。 在所示的实施例中，在接下来的含硅栅电极沉积期间，保护高k栅极电介质，例如氧化锆，以防止还原。 特别地，种子沉积阶段包括设计用于最小化栅极电介质的氢还原的条件，包括硅源气体的低氢含量，低温和/或低分压。 优选地，为了更高的沉积速率改变条件，并且在体相中继续沉积。 尽管如此，通过控制上述参数仍然使氢扩散最小化。 在一个实施例中，通过省略氢载体气体来最小化高k电介质的减小。 在另一个实施方案中，高级硅烷有助于降低给定沉积速率的氢含量。

公开(公告)号：US09659799B2

公开(公告)日：2017-05-23

申请号：US13597108

申请日：2012-08-28

申请人： Keith R. Lawson ,  Michael E. Givens

发明人： Keith R. Lawson ,  Michael E. Givens

IPC分类号： G06F19/00 ,  H01L21/67 ,  G05B19/418

CPC分类号： H01L21/67276 ,  G05B19/41885 ,  G05B2219/45031 ,  Y02P90/20 ,  Y02P90/26

摘要： Embodiments of the present disclosure can help increase throughput and reduce resource conflicts and delays in semiconductor processing tools. An exemplary method according to various aspects of the present disclosure includes analyzing, by a computer program operating on a computer system, a plurality of expected times to complete each of a respective plurality of actions to be performed by a semiconductor processing tool, the semiconductor processing tool including a first process module and a second process module.

公开(公告)号：US20140067110A1

公开(公告)日：2014-03-06

申请号：US13597108

申请日：2012-08-28

申请人： Keith R. Lawson ,  Michael E. Givens

发明人： Keith R. Lawson ,  Michael E. Givens

IPC分类号： G06F19/00

CPC分类号： H01L21/67276 ,  G05B19/41885 ,  G05B2219/45031 ,  Y02P90/20 ,  Y02P90/26

摘要： Embodiments of the present disclosure can help increase throughput and reduce resource conflicts and delays in semiconductor processing tools. An exemplary method according to various aspects of the present disclosure includes analyzing, by a computer program operating on a computer system, a plurality of expected times to complete each of a respective plurality of actions to be performed by a semiconductor processing tool, the semiconductor processing tool including a first process module and a second process module.

摘要翻译： 本公开的实施例可以有助于提高吞吐量并减少半导体处理工具中的资源冲突和延迟。 根据本公开的各个方面的示例性方法包括通过在计算机系统上操作的计算机程序来分析多个预期时间以完成由半导体处理工具执行的相应多个动作中的每一个，半导体处理 工具，其包括第一处理模块和第二处理模块。

公开(公告)号：US07122085B2

公开(公告)日：2006-10-17

申请号：US10629029

申请日：2003-07-29

申请人： Eric J. Shero ,  Michael E. Givens ,  Ryan Schmidt

发明人： Eric J. Shero ,  Michael E. Givens ,  Ryan Schmidt

IPC分类号： C23C16/448

CPC分类号： C23C16/45544 ,  C23C16/4481 ,  C23C16/4483

摘要： Preferred embodiments of the present invention provides a sublimation system employing guidance structures including certain preferred embodiments having a high surface area support medium onto which a solid source material for vapor reactant is coated. Preferably, a guidance structure is configured to facilitate the repeated saturation of the carrier gas with the solid source for a vapor reactant. Methods of saturating a carrier gas using guidance structures are also provided.

摘要翻译： 本发明的优选实施方案提供了采用引导结构的升华系统，其包括具有高表面积支持介质的某些优选实施方案，在其上涂覆用于蒸汽反应物的固体源材料。 优选地，引导结构被配置为促进载气与用于蒸汽反应物的固体源的反复饱和。 还提供了使用引导结构使载气饱和的方法。

公开(公告)号：US07026219B2

公开(公告)日：2006-04-11

申请号：US10074722

申请日：2002-02-11

申请人： Christophe F. Pomarede ,  Michael E. Givens ,  Eric J. Shero ,  Michael A. Todd

发明人： Christophe F. Pomarede ,  Michael E. Givens ,  Eric J. Shero ,  Michael A. Todd

IPC分类号： H01L21/336 ,  H01L21/20 ,  H01L21/4763 ,  H01L21/469

CPC分类号： H01L21/28194 ,  B82Y10/00 ,  C23C16/0272 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/28035 ,  H01L21/28044 ,  H01L21/28525 ,  H01L21/28556 ,  H01L29/4925 ,  H01L29/517 ,  H01L31/1804 ,  H01L31/182 ,  H01L31/202 ,  Y02E10/546 ,  Y02E10/547 ,  Y02P70/521

摘要： Methods are provided herein for forming electrode layers over high dielectric constant (“high k”) materials. In the illustrated embodiments, a high k gate dielectric, such as zirconium oxide, is protected from reduction during a subsequent deposition of silicon-containing gate electrode. In particular, a seed deposition phase includes conditions designed for minimizing hydrogen reduction of the gate dielectric, including low hydrogen content, low temperatures and/or low partial pressures of the silicon source gas. Conditions are preferably changed for higher deposition rates and deposition continues in a bulk phase. Desirably, though, hydrogen diffusion is still minimized by controlling the above-noted parameters. In one embodiment, high k dielectric reduction is minimized through omission of a hydrogen carrier gas. In another embodiment, higher order silanes aid in reducing hydrogen content for a given deposition rate.

摘要翻译： 本文提供了用于在高介电常数（“高k”）材料上形成电极层的方法。 在所示的实施例中，在接下来的含硅栅电极沉积期间，保护高k栅极电介质，例如氧化锆，以防止还原。 特别地，种子沉积阶段包括设计用于最小化栅极电介质的氢还原的条件，包括硅源气体的低氢含量，低温和/或低分压。 优选地，为了更高的沉积速率改变条件，并且在体相中继续沉积。 然而，尽管通过控制上述参数仍然使氢扩散最小化。 在一个实施例中，通过省略氢载体气体来最小化高k电介质的减小。 在另一个实施方案中，高级硅烷有助于降低给定沉积速率的氢含量。

公开(公告)号：US5354694A

公开(公告)日：1994-10-11

申请号：US79647

申请日：1993-06-18

申请人： Robert J. Field ,  Michael E. Givens ,  Mary A. Whisenant

发明人： Robert J. Field ,  Michael E. Givens ,  Mary A. Whisenant

IPC分类号： H01J1/34 ,  H01L31/18

CPC分类号： H01J1/34 ,  Y10S148/12

摘要： A negative electron affinity device has acceptor dopant concentration increased proximate the emitter face of the III-V semiconductor layer and within the depletion zone effected by an overlying CsO negative electron affinity coating. Methods to accomplish dopant concentration include diffusion, ion implantation and doping during crystal growth.

摘要翻译： 负电子亲和装置具有在III-V半导体层的发射极面附近增加的受体掺杂剂浓度，并且在覆盖的CsO负电子亲和涂层的耗尽区内。 实现掺杂剂浓度的方法包括在晶体生长期间的扩散，离子注入和掺杂。