公开(公告)号：US20070216437A1

公开(公告)日：2007-09-20

申请号：US11374850

申请日：2006-03-14

Applicant: Michael Slaughter ,  Christie Larson

Inventor： Michael Slaughter ,  Christie Larson

IPC: G01R31/26

CPC classification number: G01R31/2893 ,  G01R1/0441

Abstract: Pusher assemblies for use in microelectronic device testing systems and methods for using such pusher assemblies are disclosed herein. One particular embodiment of such a pusher assembly comprises a plate having a first side and a second side opposite the first side. An engagement assembly is removably coupled to the second side of the plate and positioned to contact a microfeature device being tested. The pusher assembly can include an urging member proximate the first side of the plate and configured to move the engagement assembly toward the device being tested. The pusher assembly can also include a heat transfer unit carried by the first side of the plate. In several embodiments, the pusher assembly can further include a plurality of pins carried by the engagement assembly such that the pins extend through the plate and engage the urging member to restrict axial movement of the urging member toward the device being tested.

Abstract translation: 用于微电子器件测试系统的推动器组件和用于使用这种推动器组件的方法在此公开。 这种推动器组件的一个具体实施例包括具有与第一侧相对的第一侧和第二侧的板。 接合组件可移除地联接到板的第二侧并且定位成接触被测试的微型特征装置。 推动器组件可以包括邻近板的第一侧的推动构件，并且构造成使接合组件朝向被测试的装置移动。 推动器组件还可以包括由板的第一侧承载的传热单元。 在几个实施例中，推动器组件还可以包括由接合组件承载的多个销，使得销延伸穿过板并接合推动构件以限制推动构件朝着被测试装置的轴向运动。

公开(公告)号：US20060197544A1

公开(公告)日：2006-09-07

申请号：US11414987

申请日：2006-05-01

Applicant: John Caldwell ,  Mark Tverdy ,  Michael Slaughter

Inventor： John Caldwell ,  Mark Tverdy ,  Michael Slaughter

IPC: G01R31/02

CPC classification number: G01R1/0483 ,  G01R31/2893

Abstract: Test sockets, test systems, and methods for testing microfeature devices with a substrate and a plurality of conductive interconnect elements projecting from the substrate. In one embodiment, a test socket includes a support surface and a plurality of apertures in the support surface corresponding to at least some of the interconnect elements of the microfeature device. The individual apertures extend through the test socket and are sized to receive a portion of one of the interconnect elements so that the substrate is spaced apart from the support surface when the microfeature device is received in the test socket. In one aspect of this embodiment, the individual apertures have a cross-sectional dimension less than a cross-sectional dimension of the interconnect elements so that the apertures receive only a portion of the corresponding interconnect element.

公开(公告)号：US20050206401A1

公开(公告)日：2005-09-22

申请号：US10805872

申请日：2004-03-22

Applicant: John Caldwell ,  Mark Tverdy ,  Michael Slaughter

Inventor： John Caldwell ,  Mark Tverdy ,  Michael Slaughter

IPC: G01R1/04 ,  G01R31/02 ,  G01R31/28

CPC classification number: G01R1/0483 ,  G01R31/2893

Abstract: Test sockets, test systems, and methods for testing microfeature devices with a substrate and a plurality of conductive interconnect elements projecting from the substrate. In one embodiment, a test socket includes a support surface and a plurality of apertures in the support surface corresponding to at least some of the interconnect elements of the microfeature device. The individual apertures extend through the test socket and are sized to receive a portion of one of the interconnect elements so that the substrate is spaced apart from the support surface when the microfeature device is received in the test socket. In one aspect of this embodiment, the individual apertures have a cross-sectional dimension less than a cross-sectional dimension of the interconnect elements so that the apertures receive only a portion of the corresponding interconnect element.

Abstract translation: 测试插座，测试系统和用于利用衬底和从衬底突出的多个导电互连元件来测试微特征器件的方法。 在一个实施例中，测试插座包括支撑表面和支撑表面中对应于微特征装置的至少一些互连元件的多个孔。 单独的孔延伸穿过测试插座，并且其尺寸被设计成接收互连元件中的一个的一部分，使得当微特征装置被接收在测试插座中时，基板与支撑表面间隔开。 在该实施例的一个方面，单个孔具有小于互连元件的横截面尺寸的横截面尺寸，使得孔仅接收相应互连元件的一部分。

公开(公告)号：US20100097090A1

公开(公告)日：2010-04-22

申请号：US12644185

申请日：2009-12-22

Applicant: Michael Slaughter ,  Christie Dyan Larson

Inventor： Michael Slaughter ,  Christie Dyan Larson

IPC: G01R31/26

CPC classification number: G01R31/2893 ,  G01R1/0441

Abstract: Pusher assemblies for use in microelectronic device testing systems and methods for using such pusher assemblies are disclosed herein. One particular embodiment of such a pusher assembly comprises a plate having a first side and a second side opposite the first side. An engagement assembly is removably coupled to the second side of the plate and positioned to contact a microfeature device being tested. The pusher assembly can include an urging member proximate the first side of the plate and configured to move the engagement assembly toward the device being tested. The pusher assembly can also include a heat transfer unit carried by the first side of the plate. In several embodiments, the pusher assembly can further include a plurality of pins carried by the engagement assembly such that the pins extend through the plate and engage the urging member to restrict axial movement of the urging member toward the device being tested.

Abstract translation: 用于微电子器件测试系统的推动器组件和用于使用这种推动器组件的方法在此公开。 这种推动器组件的一个具体实施例包括具有与第一侧相对的第一侧和第二侧的板。 接合组件可移除地联接到板的第二侧并且定位成接触被测试的微型特征装置。 推动器组件可以包括邻近板的第一侧的推动构件，并且构造成使接合组件朝向被测试的装置移动。 推动器组件还可以包括由板的第一侧承载的传热单元。 在几个实施例中，推动器组件还可以包括由接合组件承载的多个销，使得销延伸穿过板并接合推动构件以限制推动构件朝着被测试装置的轴向运动。

公开(公告)号：US07652495B2

公开(公告)日：2010-01-26

申请号：US11374850

申请日：2006-03-14

Applicant: Michael Slaughter ,  Christie Dyan Larson

Inventor： Michael Slaughter ,  Christie Dyan Larson

IPC: G01R31/26 ,  G01R31/02 ,  G01R31/28

CPC classification number: G01R31/2893 ,  G01R1/0441

Abstract: Pusher assemblies for use in microelectronic device testing systems and methods for using such pusher assemblies are disclosed herein. One particular embodiment of such a pusher assembly comprises a plate having a first side and a second side opposite the first side. An engagement assembly is removably coupled to the second side of the plate and positioned to contact a microfeature device being tested. The pusher assembly can include an urging member proximate the first side of the plate and configured to move the engagement assembly toward the device being tested. The pusher assembly can also include a heat transfer unit carried by the first side of the plate. In several embodiments, the pusher assembly can further include a plurality of pins carried by the engagement assembly such that the pins extend through the plate and engage the urging member to restrict axial movement of the urging member toward the device being tested.

Abstract translation: 用于微电子器件测试系统的推动器组件和用于使用这种推动器组件的方法在此公开。 这种推动器组件的一个具体实施例包括具有与第一侧相对的第一侧和第二侧的板。 接合组件可移除地联接到板的第二侧并且定位成接触被测试的微型特征装置。 推动器组件可以包括邻近板的第一侧的推动构件，并且构造成使接合组件朝向被测试的装置移动。 推动器组件还可以包括由板的第一侧承载的传热单元。 在几个实施例中，推动器组件还可以包括由接合组件承载的多个销，使得销延伸穿过板并接合推动构件以限制推动构件朝着被测试装置的轴向运动。

公开(公告)号：US20050206012A1

公开(公告)日：2005-09-22

申请号：US10801205

申请日：2004-03-16

Applicant: Warren Farnworth ,  William Hiatt ,  Tim Murphy ,  John Caldwell ,  Michael Slaughter ,  David Hembree ,  Jamie Wanke

Inventor： Warren Farnworth ,  William Hiatt ,  Tim Murphy ,  John Caldwell ,  Michael Slaughter ,  David Hembree ,  Jamie Wanke

IPC: H01L21/56 ,  H01L23/48 ,  H01L23/485

CPC classification number: H01L24/06 ,  H01L21/563 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/73203 ,  H01L2224/73257 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2224/45099

Abstract: Stress and force management techniques for a semiconductor die to help compensate for stress within the semiconductor die and to help compensate for forces applied to the semiconductor die to minimize damage thereto.

Abstract translation: 用于半导体管芯的应力和力管理技术来帮助补偿半导体管芯内的应力，并帮助补偿施加到半导体管芯上的力以最小化对其的损害。

公开(公告)号：US06233172B1

公开(公告)日：2001-05-15

申请号：US09464807

申请日：1999-12-17

Applicant: Eugene Youjun Chen ,  Jon Michael Slaughter ,  Mark Durlam ,  Mark DeHerrera ,  Saied N. Tehrani

Inventor： Eugene Youjun Chen ,  Jon Michael Slaughter ,  Mark Durlam ,  Mark DeHerrera ,  Saied N. Tehrani

IPC: G11C1115

CPC classification number: H01F10/3254 ,  B82Y25/00 ,  G11C11/16 ,  H01F10/3272

Abstract: An improved and novel magnetic element (10; 10′; 50; 50′; 80) including a plurality of thin film layers wherein the bit end magneto-static demagnetizing fields cancel the total positive coupling of the structure to obtain dual magnetic states in a zero external field. Additionally disclosed is a method of fabricating a magnetic element (10) by providing a plurality of thin film layers wherein the bit end magneto-static demagnetizing fields of the thin film layers cancel the total positive coupling of the structure to obtain dual magnetic states in a zero external field.

Abstract translation: 包括多个薄膜层的改进和新颖的磁性元件（10; 10'; 50; 50'; 80），其中所述位端磁静电消磁场抵消所述结构的总正耦合以获得双重磁状态 零外场。 另外公开了一种通过提供多个薄膜层来制造磁性元件（10）的方法，其中薄膜层的位端磁静电消磁场抵消该结构的总正耦合以获得双重磁状态 零外场。

公开(公告)号：US06211090B1

公开(公告)日：2001-04-03

申请号：US09528971

申请日：2000-03-21

Applicant: Mark Durlam ,  Eugene Youjun Chen ,  Saied N. Tehrani ,  Jon Michael Slaughter ,  Gloria Kerszykowski ,  Kelly Wayne Kyler

Inventor： Mark Durlam ,  Eugene Youjun Chen ,  Saied N. Tehrani ,  Jon Michael Slaughter ,  Gloria Kerszykowski ,  Kelly Wayne Kyler

IPC: H01L2100

CPC classification number: H01L27/222 ,  B82Y10/00

Abstract: A method of fabricating a flux concentrator for use in magnetic memory devices including the steps of providing at least one magnetic memory bit (10) and forming proximate thereto a material stack defining a copper (Cu) damascene bit line (56) including a flux concentrating layer (52). The method includes the steps of depositing a bottom dielectric layer (32), an optional etch stop (34) layer, and a top dielectric layer (36) proximate the magnetic memory bit (10). A trench (38) is etched in the top dielectric layer (36) and the bottom dielectric layer (32). A first barrier layer (42) is deposited in the trench (38). Next, a metal system (29) is deposited on a surface of the first barrier layer (42). The metal system (29) includes a copper (Cu) seed material (44), and a plated copper (Cu) material (46), a first outside barrier layer (50), a flux concentrating layer (52), and a second outside barrier layer (54). The metal system (29) is patterned and etched to define a copper (Cu) damascene bit line (56).

Abstract translation: 一种制造用于磁存储器件的通量集中器的方法，包括以下步骤：提供至少一个磁存储器位（10），并在其附近形成限定铜（Cu）镶嵌位线（56）的材料堆，所述铜（Cu）镶嵌位线包括通量集中 层（52）。 该方法包括以下步骤：沉积底部电介质层（32），可选的蚀刻停止层（34）层和靠近磁存储器位（10）的顶部电介质层（36）。 在顶部电介质层（36）和底部电介质层（32）中蚀刻沟槽（38）。 第一阻挡层（42）沉积在沟槽（38）中。 接下来，金属系统（29）沉积在第一阻挡层（42）的表面上。 金属系统（29）包括铜（Cu）种子材料（44）和镀铜（Cu）材料（46），第一外部阻挡层（50），集流层（52）和第二 外部阻挡层（54）。 金属系统（29）被图案化和蚀刻以限定铜（Cu）镶嵌位线（56）。

公开(公告)号：US06376260B1

公开(公告)日：2002-04-23

申请号：US09825705

申请日：2001-04-05

Applicant: Eugene Youjun Chen ,  Jon Michael Slaughter ,  Jing Shi

Inventor： Eugene Youjun Chen ,  Jon Michael Slaughter ,  Jing Shi

IPC: H01L2100

CPC classification number: H01F41/307 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3268 ,  H01F10/3272 ,  H01L43/08

Abstract: An improved and novel fabrication method for a magnetic element, and more particularly a magnetic element (10) including a first electrode (14) , a second electrode (18) and a spacer layer (16). The first electrode (14) includes a fixed ferromagnetic layer (26) having a thickness t1. A second electrode (18) is included and comprises a free ferromagnetic layer (28) having a thickness t2. A spacer layer (16) is located between the fixed ferromagnetic layer (26) and the free ferromagnetic (28) layer, the spacer layer (16) having a thickness t3, where 0.25t3

Abstract translation: 一种用于磁性元件的改进和新颖的制造方法，更具体地，包括第一电极（14），第二电极（18）和间隔层（16）的磁性元件（10）。 第一电极（14）包括具有厚度t1的固定铁磁层（26）。 包括第二电极（18）并且包括具有厚度t2的自由铁磁层（28）。 间隔层（16）位于固定铁磁层（26）和自由铁磁层（28）之间，隔离层（16）的厚度为t3，其中0.25t3

公开(公告)号：US06292389B1

公开(公告)日：2001-09-18

申请号：US09356864

申请日：1999-07-19

Applicant: Eugene Youjun Chen ,  Jon Michael Slaughter ,  Jing Shi

Inventor： Eugene Youjun Chen ,  Jon Michael Slaughter ,  Jing Shi

IPC: H01L2976

CPC classification number: H01F41/307 ,  B82Y10/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/3268 ,  H01F10/3272 ,  H01L43/08

Abstract: An improved and novel fabrication method for a magnetic element, and more particularly a magnetic element (10) including a first electrode (14), a second electrode (18) and a spacer layer (16). The first electrode (14) includes a fixed ferromagnetic layer (26) having a thickness t1. A second electrode (18) is included and comprises a free ferromagnetic layer (28) having a thickness t2. A spacer layer (16) is located between the fixed ferromagnetic layer (26) and the free ferromagnetic (28) layer, the spacer layer (16) having a thickness t3, where 0.25t3

Abstract translation: 一种用于磁性元件的改进和新颖的制造方法，更具体地，包括第一电极（14），第二电极（18）和间隔层（16）的磁性元件（10）。 第一电极（14）包括具有厚度t1的固定铁磁层（26）。 包括第二电极（18）并且包括具有厚度t2的自由铁磁层（28）。 间隔层（16）位于固定铁磁层（26）和自由铁磁层（28）之间，隔离层（16）的厚度为t3，其中0.25t3