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    METHOD OF FORMING FINNED SEMICONDUCTOR DEVICES WITH TRENCH ISOLATION
    1.
    发明申请
    METHOD OF FORMING FINNED SEMICONDUCTOR DEVICES WITH TRENCH ISOLATION 有权
    形成具有热分解的微结构半导体器件的方法

    公开(公告)号：US20100015778A1

    公开(公告)日：2010-01-21

    申请号：US12176866

    申请日：2008-07-21

    申请人： Ming-ren LIN ,  Zoran KRIVOKAPIC ,  Witek MASZARA

    发明人： Ming-ren LIN ,  Zoran KRIVOKAPIC ,  Witek MASZARA

    IPC分类号： H01L21/76

    CPC分类号： H01L21/823431 ,  H01L21/76232 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7851

    摘要： A method of manufacturing a semiconductor device structure, such as a FinFET device structure, is provided. The method begins by providing a substrate comprising a bulk semiconductor material, a first conductive fin structure formed from the bulk semiconductor material, and a second conductive fin structure formed from the bulk semiconductor material. The first conductive fin structure and the second conductive fin structure are separated by a gap. Next, spacers are formed in the gap and adjacent to the first conductive fin structure and the second conductive fin structure. Thereafter, an etching step etches the bulk semiconductor material, using the spacers as an etch mask, to form an isolation trench in the bulk semiconductor material. A dielectric material is formed in the isolation trench, over the spacers, over the first conductive fin structure, and over the second conductive fin structure. Thereafter, at least a portion of the dielectric material and at least a portion of the spacers are etched away to expose an upper section of the first conductive fin structure and an upper section of the second conductive fin structure, while preserving the dielectric material in the isolation trench. Following these steps, the fabrication of the devices is completed in a conventional manner.

    摘要翻译： 提供了诸如FinFET器件结构的半导体器件结构的制造方法。 该方法开始于提供包括体半导体材料的衬底，由体半导体材料形成的第一导电鳍结构以及由体半导体材料形成的第二导电鳍结构。 第一导电鳍结构和第二导电鳍结构被间隙分开。 接下来，间隔件形成在间隙中并且与第一导电翅片结构和第二导电翅片结构相邻。 此后，蚀刻步骤使用间隔物作为蚀刻掩模来蚀刻体半导体材料，以在体半导体材料中形成隔离沟槽。 绝缘材料形成在隔离沟槽中，在间隔物之上，在第一导电鳍结构之上，并在第二导电鳍结构之上。 此后，介电材料的至少一部分和至少一部分间隔物被蚀刻掉以露出第一导电鳍结构的上部和第二导电翅片结构的上部，同时将介电材料保留在 隔离沟 按照这些步骤，以常规方式完成装置的制造。

    FULLY SILICIDED GATE STRUCTURE FOR FINFET DEVICES
    4.
    发明申请
    FULLY SILICIDED GATE STRUCTURE FOR FINFET DEVICES 有权
    FINFET器件的完全硅胶结构

    公开(公告)号：US20060177998A1

    公开(公告)日：2006-08-10

    申请号：US11379435

    申请日：2006-04-20

    申请人： Ming-Ren Lin ,  Witold Maszara ,  Haihong Wang ,  Bin Yu

    发明人： Ming-Ren Lin ,  Witold Maszara ,  Haihong Wang ,  Bin Yu

    IPC分类号： H01L21/3205

    CPC分类号： H01L29/785 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/7842

    摘要： A method may include forming a gate electrode over a fin structure, depositing a first metal layer on a top surface of the gate electrode, performing a first silicide process to convert a portion of the gate electrode into a metal-silicide compound, depositing a second metal layer on a top surface of the metal-silicide compound, and performing a second silicide process to form a fully-silicided gate electrode.

    摘要翻译： 一种方法可以包括在鳍结构上形成栅电极，在栅电极的顶表面上沉积第一金属层，执行第一硅化工艺以将栅电极的一部分转化为金属硅化物， 在金属硅化物化合物的顶表面上的金属层，并且执行第二硅化物处理以形成全硅化物栅电极。

    Semiconductor on insulator MOSFET having strained silicon channel
    5.
    发明授权
    Semiconductor on insulator MOSFET having strained silicon channel 有权
    具有应变硅沟道的半导体绝缘体MOSFET

    公开(公告)号：US06943087B1

    公开(公告)日：2005-09-13

    申请号：US10738529

    申请日：2003-12-17

    申请人： Qi Xiang ,  Jung-Suk Goo ,  James N. Pan ,  Ming Ren Lin

    发明人： Qi Xiang ,  Jung-Suk Goo ,  James N. Pan ,  Ming Ren Lin

    IPC分类号： H01L21/331 ,  H01L21/8222

    CPC分类号： H01L29/66545 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78654

    摘要： Strained silicon is grown on a dielectric material in a trench in a silicon germanium layer at a channel region of a MOSFET after fabrication of other MOSFET elements using a removable dummy gate process to form an SOI MOSFET. The MOSFET is fabricated with the dummy gate in place, the dummy gate is removed, and a trench is formed in the channel region. Dielectric material is grown in the trench, and strained silicon is then grown from the silicon germanium trench sidewalls to form a strained silicon layer that extends across the dielectric material. The silicon germanium sidewalls impart strain to the strained silicon, and the presence of the dielectric material allows the strained silicon to be grown as a thin fully depleted layer. A replacement gate is then formed by damascene processing.

    摘要翻译： 在使用可移除的虚拟栅极工艺制造其它MOSFET元件以形成SOI MOSFET之后，将应变硅在MOSFET的沟道区的硅锗层中的沟槽中的电介质材料上生长。 MOSFET由虚拟栅极制造在位，虚拟栅极被去除，并且在沟道区域中形成沟槽。 电介质材料在沟槽中生长，然后从硅锗沟槽侧壁生长应变硅，以形成延伸穿过电介质材料的应变硅层。 硅锗侧壁对应变硅施加应变，并且电介质材料的存在允许应变硅作为薄的完全耗尽层生长。 然后通过镶嵌加工形成替换浇口。

    Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric
    8.
    发明授权
    Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric 有权
    具有高K电介质的半导体器件具有渐变介电常数的间隔物

    公开(公告)号：US06764966B1

    公开(公告)日：2004-07-20

    申请号：US10085278

    申请日：2002-02-27

    申请人： William George En ,  Arvind Halliyal ,  Ming-Ren Lin ,  Minh Van Ngo ,  Chih-Yuh Yang

    发明人： William George En ,  Arvind Halliyal ,  Ming-Ren Lin ,  Minh Van Ngo ,  Chih-Yuh Yang

    IPC分类号： H01L2128

    CPC分类号： H01L29/6656 ,  H01L29/66833 ,  H01L29/78

    摘要： A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a dielectric layer interposed between a gate electrode and the semiconductor substrate. Further, the semiconductor device includes graded dielectric constant spacers formed on sidewalls of the dielectric layer, sidewalls of the gate electrode and portions of an upper surface of the semiconductor substrate. The dielectric constant of the graded dielectric constant spacers decreases in a direction away from the sidewalls of the dielectric layer.

    摘要翻译： 公开了一种形成在具有有源区的半导体衬底上的半导体器件及其制造方法。 半导体器件包括插入在栅电极和半导体衬底之间的电介质层。 此外，半导体器件包括形成在电介质层的侧壁，栅电极的侧壁和半导体衬底的上表面的部分上的渐变介电常数间隔物。 梯度介电常数间隔物的介电常数在远离介电层的侧壁的方向上减小。

    Transistor with local insulator structure
    9.
    发明授权
    Transistor with local insulator structure 失效
    具有局部绝缘体结构的晶体管

    公开(公告)号：US06670260B1

    公开(公告)日：2003-12-30

    申请号：US09577332

    申请日：2000-05-24

    申请人： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

    发明人： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

    IPC分类号： H01L21425

    CPC分类号： H01L29/6659 ,  H01L29/0649 ,  H01L29/78

    摘要： A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

    摘要翻译： 薄膜完全耗尽的绝缘体上硅（SOI）金属氧化物半导体场缺陷晶体管（MOSFET）利用局部绝缘结构。 局部绝缘结构包括沟道区下方的埋置二氧化硅区域。 MOSFET体的厚度非常小，而在沟道区域和掩埋的二氧化硅区域之外可用的硅可用于源极和漏极区域中足够的硅化物深度。 掩埋的二氧化硅区域可以通过沟槽隔离技术或LOCOS技术形成。

    Method of manufacturing a dual doped CMOS gate
    10.
    发明授权
    Method of manufacturing a dual doped CMOS gate 有权
    制造双掺杂CMOS栅极的方法

    公开(公告)号：US06342438B2

    公开(公告)日：2002-01-29

    申请号：US09187379

    申请日：1998-11-06

    申请人： Bin Yu ,  Ming-Ren Lin

    发明人： Bin Yu ,  Ming-Ren Lin

    IPC分类号： H01L21265

    CPC分类号： H01L21/823842 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823871

    摘要： A dual doped CMOS gate structure utilizes a nitrogen implant to suppress dopant inter-diffusion. The nitrogen implant is provided above standard trench isolation structures. Alternatively, an oxygen implant can be utilized. The use of the implant allows an increase in packing density for ultra-large-scale integrated (ULSI) circuits. The doping for N-channel and P-channel active regions can be completed when the polysilicon gate structures are doped.

    摘要翻译： 双掺杂CMOS栅极结构利用氮注入来抑制掺杂剂相互扩散。 在标准沟槽隔离结构之上提供氮注入。 或者，可以使用氧注入。 使用植入物可以提高超大规模集成（ULSI）电路的封装密度。 当掺杂多晶硅栅极结构时，可以完成N沟道和P沟道有源区的掺杂。