Electronic part having communication means
    1.
    发明授权
    Electronic part having communication means 失效
    电子部件具有通讯装置

    公开(公告)号:US5978203A

    公开(公告)日:1999-11-02

    申请号:US831966

    申请日:1997-04-02

    CPC分类号: H01G4/224 H01G9/12

    摘要: An electronic part such as a ceramic capacitor and a resistor used in various kinds of electric appliances has an apprehension that an electronic part element might be red-heated to be burnt when an abnormal current flows in spite of dielectric covering member, and therefore it has been impossible to supply a nonflammable electronic part having a stabilized performance. In the present invention, an electronic part is constructed such that since an electronic part element 8 such as a condenser or a resistor is put in a case 5 which in turn is nearly sealed to cut off the supply of oxygen, the electronic part is prevented from catching fire even if it generates heat, and since an opening 6 is formed in a portion of the case 5 or a sealing member 7 so as to allow the gas to be let out, when the electronic part generates heat to increase the pressure, the case 5 can be prevented from being ruptured. Accordingly, it is possible to provide a nonflammable electronic part having stabilized characteristics.

    摘要翻译: 担心在各种电器中使用的诸如陶瓷电容器和电阻器的电子部件担心尽管电介质覆盖部件异常电流流动时电子部件可能被红色加热而被烧焦,因此它具有 不可能提供具有稳定性能的不可燃电子部件。 在本发明中,电子部件被构造为使得诸如电容器或电阻器的电子部件元件8被放入壳体5中,壳体5又被几乎密封以切断供氧,所以防止了电子部件 即使产生热量也能够起火,并且由于在壳体5的一部分或密封部件7中形成开口6以允许气体被排出,所以当电子部件产生热量以增加压力时, 可以防止壳体5破裂。 因此,可以提供具有稳定特性的不可燃电子部件。

    METHOD AND APPARATUS FOR DISPLAYING BATCH EXECUTION DATA OF AN INDUSTRIAL PLANT
    3.
    发明申请
    METHOD AND APPARATUS FOR DISPLAYING BATCH EXECUTION DATA OF AN INDUSTRIAL PLANT 审中-公开
    用于显示工业厂房批量执行数据的方法和装置

    公开(公告)号:US20110289450A1

    公开(公告)日:2011-11-24

    申请号:US12785022

    申请日:2010-05-21

    IPC分类号: G06F3/048

    摘要: A method and apparatus for displaying batch execution data of an industrial plant configured for performing a plurality of batch executions. The method comprises selecting a first level element in a first level window; and displaying in a second level window all second level elements comprised by the selected first level element, the second level window being displayed within the first level window directly beneath the selected first level element without obscuring any other first level element in the first level window. The apparatus comprises a window display module configured for displaying at least one second level window within a first level window such that upon selection of a first level element in the first level window, a corresponding second level window is displayed within the first level window directly beneath its corresponding first level element without obscuring any other first level element in the first level window, each second level window displaying all second level elements comprised by its corresponding first level element.

    摘要翻译: 一种用于显示被配置用于执行多个批处理的工厂的批处理执行数据的方法和装置。 该方法包括在第一级窗口中选择第一级元素; 并且在第二级窗口中显示由所选择的第一级元素包括的所有第二级元素,所述第二级窗口在所述第一级元素的正下方显示在所述第一级窗口内,而不会遮蔽所述第一级窗口中的任何其它第一级元素。 该装置包括一个窗口显示模块,该窗口显示模块被配置为在第一级窗口内显示至少一个第二级窗口,使得在第一级窗口中选择第一级元件后,在第一级窗口内直接显示对应的第二级窗口 其对应的第一级元素而不遮蔽第一级窗口中的任何其他第一级元素,每个第二级窗口显示由其对应的第一级元素包括的所有第二级元素。

    Semiconductor integrated circuit
    5.
    发明申请
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号:US20100207662A1

    公开(公告)日:2010-08-19

    申请号:US12656667

    申请日:2010-02-12

    IPC分类号: H03K19/00

    CPC分类号: G01R31/31858 G01R31/31725

    摘要: An exemplary aspect of the invention is to conduct delay tests under actual operating conditions for a semiconductor integrated circuit including multiple logic circuits operating based on clocks of different frequencies, without causing any inconveniences when a test clock is set to a high-frequency side or a low-frequency side. The semiconductor integrated circuit includes: a first logic block that operates based on a first clock; a second logic block that operates based on a second clock having a frequency different from that of the first clock; and a test circuit connected between the first logic block and the second logic block. The test circuit outputs an output of the first logic block set as a test target, without passing through the second logic block, and transmits an input value received without being passed through the first logic circuit, to the second logic circuit set as a test target.

    摘要翻译: 本发明的示例性方面是在实际操作条件下进行包括基于不同频率的时钟操作的多个逻辑电路的半导体集成电路的延迟测试,而不会在将测试时钟设置为高频侧或 低频侧。 半导体集成电路包括:基于第一时钟操作的第一逻辑块; 基于具有与第一时钟的频率不同的频率的第二时钟来操作的第二逻辑块; 以及连接在第一逻辑块和第二逻辑块之间的测试电路。 测试电路输出作为测试对象的第一逻辑块的输出,而不通过第二逻辑块,并将接收的输入值传送到不经第一逻辑电路的第二逻辑电路作为测试对象 。

    Generating a relation diagram of data files
    6.
    发明授权
    Generating a relation diagram of data files 有权
    生成数据文件的关系图

    公开(公告)号:US07747621B2

    公开(公告)日:2010-06-29

    申请号:US11012100

    申请日:2004-12-16

    IPC分类号: G06F7/00 G06F17/30 G06F3/048

    CPC分类号: G06F17/30011

    摘要: The invention provides a system that associates data files with one another effectively to visually represent a relation among the data files and allows a user to easily understand relationship of contents of the data files. The system determines whether there is a parent data file for a selected retrieval object data file with reference to a contract association table and, if the parent data file is present, changes the retrieval object to the parent data file and repeats the processing. If the parent data file is not present, the system stores a present retrieval object data file as display data, that is, store a top data file as display data. Then, the system retrieves all data files associated with the top data file, stores the data files as display data, generates a relation diagram of the data files, and transmits the relation diagram to a user terminal.

    摘要翻译: 本发明提供了一种将数据文件彼此有效地相关联以可视地表示数据文件之间的关系的系统,并且允许用户容易地理解数据文件的内容的关系。 该系统参照合同关联表确定所选检索对象数据文件是否存在父数据文件,如果存在父数据文件,则将检索对象改变为父数据文件并重复该处理。 如果不存在父数据文件,则系统将当前检索对象数据文件存储为显示数据,即存储顶部数据文件作为显示数据。 然后,系统检索与顶部数据文件相关联的所有数据文件,将数据文件存储为显示数据,生成数据文件的关系图,并将关系图发送到用户终端。

    Array substrate for flat display device
    7.
    发明授权
    Array substrate for flat display device 有权
    平板显示器用阵列基板

    公开(公告)号:US07446759B2

    公开(公告)日:2008-11-04

    申请号:US10541552

    申请日:2004-05-28

    IPC分类号: G06F3/038 G09G3/36

    摘要: An object of this array substrate for a flat display device is to eliminate display unevenness caused by the inequality of parasitic capacitances of switches of signal line switch circuits. Electrode patterns (P) which connects the gate electrodes of the switches (ASW) to any one of a plurality of switch control signal lines (ASWL1 and ASWL2) are formed so as to each two-dimensionally overlap all of the switch control signal lines ASWL and to have substantially identical shapes, thus equalizing the areas of the electrode patterns (P).

    摘要翻译: 用于平面显示装置的该阵列基板的目的是消除由信号线开关电路的开关的寄生电容的不等式引起的显示不均匀。 形成将开关(ASW)的栅极连接到多个开关控制信号线(ASWL 1和ASWL 2)中的任一个的电极图案(P),以便将所有的开关控制信号二维地重叠 线ASWL并且具有基本相同的形状,从而均衡电极图案(P)的面积。

    Data transferring apparatus and data transferring method that use fast ring connection
    8.
    发明授权
    Data transferring apparatus and data transferring method that use fast ring connection 失效
    数据传输装置和数据传输方法,使用快速环连接

    公开(公告)号:US07020148B1

    公开(公告)日:2006-03-28

    申请号:US09712555

    申请日:2000-11-14

    IPC分类号: H04L12/28 H04L12/43

    CPC分类号: G06F13/37 H04L12/43

    摘要: A data transferring apparatus includes a ring bus, which circularly transfers data by holding in a slot to one direction and a plurality of nodes connected to the ring bus. Each of the plurality of nodes includes a detector and a controller. The detector detects whether or not data destined for a self-node is held in a slot arrived to another node connected to an upstream side of the self-node. The controller captures the data destined for the self-node from the slot when the detector detects presence of the data destined for the self-node and the slot arrives to the self-node.

    摘要翻译: 数据传送装置包括环形总线,环形总线通过将时隙保持在一个方向上而循环地传送数据,并且多个节点连接到环形总线。 多个节点中的每一个包括检测器和控制器。 检测器检测去往自身节点的数据是否保持在到达连接到自节点的上游侧的另一节点的时隙中。 当检测器检测到目的地为自节点的数据的存在并且时隙到达自节点时,控制器从时隙捕获去往自身节点的数据。

    Semiconductor integrated circuit
    9.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号:US07902856B2

    公开(公告)日:2011-03-08

    申请号:US12656667

    申请日:2010-02-12

    IPC分类号: H03K19/003 G01R31/28

    CPC分类号: G01R31/31858 G01R31/31725

    摘要: An exemplary aspect of the invention is to conduct delay tests under actual operating conditions for a semiconductor integrated circuit including multiple logic circuits operating based on clocks of different frequencies, without causing any inconveniences when a test clock is set to a high-frequency side or a low-frequency side. The semiconductor integrated circuit includes: a first logic block that operates based on a first clock; a second logic block that operates based on a second clock having a frequency different from that of the first clock; and a test circuit connected between the first logic block and the second logic block. The test circuit outputs an output of the first logic block set as a test target, without passing through the second logic block, and transmits an input value received without being passed through the first logic circuit, to the second logic circuit set as a test target.

    摘要翻译: 本发明的示例性方面是在实际操作条件下进行包括基于不同频率的时钟操作的多个逻辑电路的半导体集成电路的延迟测试,而不会在将测试时钟设置为高频侧或 低频侧。 半导体集成电路包括:基于第一时钟操作的第一逻辑块; 基于具有与第一时钟的频率不同的频率的第二时钟来操作的第二逻辑块; 以及连接在第一逻辑块和第二逻辑块之间的测试电路。 测试电路输出作为测试目标的第一逻辑块的输出,而不通过第二逻辑块,并将接收的输入值传送到不经第一逻辑电路的第二逻辑电路,作为测试目标 。

    Array substrate for flat display device
    10.
    发明申请
    Array substrate for flat display device 有权
    平板显示器用阵列基板

    公开(公告)号:US20060114202A1

    公开(公告)日:2006-06-01

    申请号:US10541552

    申请日:2004-05-28

    IPC分类号: G09G3/36

    摘要: An object of this array substrate for a flat display device is to eliminate display unevenness caused by the inequality of parasitic capacitances of switches of signal line switch circuits. Electrode patterns (P) which connects the gate electrodes of the switches (ASW) to any one of a plurality of switch control signal lines (ASWL1 and ASWL2) are formed so as to each two-dimensionally overlap all of the switch control signal lines ASWL and to have substantially identical shapes, thus equalizing the areas of the electrode patterns (P).

    摘要翻译: 用于平面显示装置的该阵列基板的目的是消除由信号线开关电路的开关的寄生电容的不等式引起的显示不均匀。 形成将开关(ASW)的栅极连接到多个开关控制信号线(ASWL 1和ASWL 2)中的任一个的电极图案(P),以便将所有的开关控制信号二维地重叠 线ASWL并且具有基本相同的形状,从而均衡电极图案(P)的面积。