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公开(公告)号：US08971091B2
公开(公告)日：2015-03-03
申请号：US13884140
申请日：2011-01-31
CPC分类号： G11C13/0069 , G11C13/0007 , G11C2013/0066 , G11C2013/0078 , G11C2213/32 , G11C2213/55 , G11C2213/77 , G11C2213/81 , H01L27/101
摘要： A method of switching a memristive device in a two-dimensional array senses a leakage current through the two-dimensional array when a voltage of half of a switching voltage is applied to a row line of the memristive device. A leakage compensation current is generated according to the sensed leakage current, and a switching current ramp is also generated. The leakage compensation current and the switching current ramp are combined to form a combined switching current, which is applied to the row line of the memristive device. When a resistance of the memristive device reaches a target value, the combined switching current is removed from the row line.
摘要翻译： 当二维阵列中的忆阻器件的切换被施加到忆阻器件的行线上时，通过二维阵列切换忆阻器件的方法来感测通过二维阵列的漏电流。 根据检测到的漏电流产生泄漏补偿电流，并且还产生开关电流斜坡。 泄漏补偿电流和开关电流斜坡组合形成组合开关电流，其被施加到忆阻器件的行线。 当忆阻器件的电阻达到目标值时，组合的开关电流从行线上去除。
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公开(公告)号：US20130106462A1
公开(公告)日：2013-05-02
申请号：US13281438
申请日：2011-10-26
IPC分类号： H03K19/177
CPC分类号： H03K19/177
摘要： A field-programmable analog array (FPAA) includes a digital signal routing network, an analog signal routing network, switch elements to interconnect the digital signal routing network with the analog signal routing network, and a configurable analog block (CAB) connected to the analog signal routing network and having a programmable resistor array. The switch elements are implemented via digital memristors, the programmable resistor array is implemented via analog memristors, and/or antifuses within one or more of the digital signal routing network and the analog signal routing network are implemented via digital memristors.
摘要翻译： 现场可编程模拟阵列（FPAA）包括数字信号路由网络，模拟信号路由网络，将数字信号路由网络与模拟信号路由网络互连的开关元件，以及连接到模拟信号的可配置模拟块（CAB） 信号路由网络并具有可编程电阻器阵列。 开关元件通过数字忆阻器实现，可编程电阻器阵列通过模拟忆阻器实现，并且/或数字信号路由网络和模拟信号路由网络内的反熔丝通过数字忆阻器来实现。
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3.发明申请PROGRAMMABLE CURRENT-LIMITED VOLTAGE BUFFER, INTEGRATED-CIRCUIT DEVICE AND METHOD FOR CURRENT-LIMITING A MEMORY ELEMENT 有权可编程电流有限电压缓冲器，集成电路设备和限制存储元件的方法公开(公告)号：US20130070534A1
公开(公告)日：2013-03-21
申请号：US13384885
申请日：2010-04-30
IPC分类号： G11C7/10
CPC分类号： G11C7/12 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0028 , G11C13/0069 , G11C27/005 , G11C27/024 , G11C2013/0073 , G11C2013/0078
摘要： A programmable current-limited voltage buffer 130-1. The programmable current-limited voltage buffer 130-1 includes at least one current-bias circuit 230-1, an inverter 230-2, a write-current set control circuit 230-3, and an adaptive current limiter 230-4. The inverter 230-2 is coupled to the current-bias circuit 230-1 and a reference-voltage source 178, and is configured to couple a row line 140-1 to either the current-bias circuit 230-1, or the reference-voltage source 178, in response to an input signal. The adaptive current limiter 230-4 is coupled to the current-bias circuit 230-1 and to the write-current set control circuit 230-3, and is configured to limit current flowing through the memory element 120-1 in a write operation. An integrated circuit device 110 is also provided, along with a method for current limiting a memory element 120-1 during switching in an array 120 of memory elements.
摘要翻译： 可编程限流电压缓冲器130-1。 可编程限流电压缓冲器130-1包括至少一个电流偏置电路230-1，反相器230-2，写入电流设置控制电路230-3和自适应限流器230-4。 反相器230-2耦合到电流偏置电路230-1和参考电压源178，并被配置为将行线140-1耦合到电流偏置电路230-1或参考电压源178。 电压源178响应输入信号。 自适应限流器230-4耦合到电流偏置电路230-1和写入电流设置控制电路230-3，并且被配置为在写入操作中限制流过存储器元件120-1的电流。 还提供集成电路装置110以及用于在切换存储元件的阵列120期间电流限制存储元件120-1的方法。
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4.发明授权公开(公告)号：US08111494B2
公开(公告)日：2012-02-07
申请号：US12695995
申请日：2010-01-28
CPC分类号： G11C13/0059 , G11C13/0002
摘要： A memristor-protection integrated circuit. The memristor-protection integrated circuit includes a first current-bias circuit, a second current-bias circuit, an inverter, and a current limiter. The first and second current-bias circuits are configured to be coupled to first and second power-supply rails, respectively. The inverter is coupled to the first current-bias circuit and to the second current-bias circuit, and is configured to couple at least one memristor to at least one of the first current-bias circuit and the second current-bias circuit in response to an input signal applied to the inverter. The current limiter is coupled to the first current-bias circuit and coupled to the second current-bias circuit, and is configured to limit current flowing through the memristor.
摘要翻译： 忆阻器保护集成电路。 避雷器保护集成电路包括第一电流偏置电路，第二电流偏置电路，反相器和限流器。 第一和第二电流偏置电路分别被配置为耦合到第一和第二电源轨。 反相器耦合到第一电流偏置电路和第二电流偏置电路，并且被配置为响应于第一电流偏置电路和第二电流偏置电路将至少一个阻电器耦合到第一电流偏置电路和第二电流偏置电路中的至少一个 施加到逆变器的输入信号。 电流限制器耦合到第一电流偏置电路并且耦合到第二电流偏置电路，并且被配置为限制流过忆阻器的电流。
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5.发明申请公开(公告)号：US20110181347A1
公开(公告)日：2011-07-28
申请号：US12695995
申请日：2010-01-28
IPC分类号： G05F1/10
CPC分类号： G11C13/0059 , G11C13/0002
摘要： A memristor-protection integrated circuit. The memristor-protection integrated circuit includes a first current-bias circuit, a second current-bias circuit, an inverter, and a current limiter. The first and second current-bias circuits are configured to be coupled to first and second power-supply rails, respectively. The inverter is coupled to the first current-bias circuit and to the second current-bias circuit, and is configured to couple at least one memristor to at least one of the first current-bias circuit and the second current-bias circuit in response to an input signal applied to the inverter. The current limiter is coupled to the first current-bias circuit and coupled to the second current-bias circuit, and is configured to limit current flowing through the memristor.
摘要翻译： 忆阻器保护集成电路。 避雷器保护集成电路包括第一电流偏置电路，第二电流偏置电路，反相器和限流器。 第一和第二电流偏置电路分别被配置为耦合到第一和第二电源轨。 反相器耦合到第一电流偏置电路和第二电流偏置电路，并且被配置为响应于第一电流偏置电路和第二电流偏置电路将至少一个阻电器耦合到第一电流偏置电路和第二电流偏置电路中的至少一个 施加到逆变器的输入信号。 电流限制器耦合到第一电流偏置电路并且耦合到第二电流偏置电路，并且被配置为限制流过忆阻器的电流。
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公开(公告)号：US20120236623A1
公开(公告)日：2012-09-20
申请号：US13050349
申请日：2011-03-17
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/004 , G11C13/0061
摘要： A memory device capable of being sensed with an oscillating signal includes a first terminal of a memristive element connected to an oscillating signal supply, and a second terminal of the memristive element connected to sensing circuitry, the sensing circuitry to determine an attenuation of an oscillating signal from the oscillating signal supply. A crossbar array includes a first set of parallel lines selectively connected to an oscillating signal supply, a second set of parallel lines intersecting the first set of parallel lines, the second set of parallel lines selectively connected to sensing circuitry, memristive memory elements being disposed at crosspoints between the first set of parallel lines and the second set of parallel lines, in which a memory controller of the crossbar array is to determine a resistive state of one of the memory elements by determining, with the sensing circuitry, an attenuation of an oscillating signal produced by the oscillating signal supply.
摘要翻译： 能够用振荡信号感测的存储器件包括连接到振荡信号电源的忆阻元件的第一端子和连接到感测电路的忆阻元件的第二端子，感测电路确定振荡信号的衰减 来自振荡信号源。 交叉开关阵列包括选择性地连接到振荡信号电源的第一组并行线，与第一组并行线相交的第二组并行线，第二组并行线选择性地连接到感测电路，忆阻存储器元件设置在 第一组平行线和第二组并行线之间的交叉点，其中交叉开关阵列的存储器控制器将通过使用感测电路确定振荡器的衰减来确定存储器元件之一的电阻状态 由振荡信号源产生的信号。
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7.发明授权Biasing circuitry for generating bias current insensitive to process, temperature and supply voltage variations 有权用于产生对过程，温度和电源电压变化不敏感的偏置电流的偏置电路公开(公告)号：US06741119B1
公开(公告)日：2004-05-25
申请号：US10231811
申请日：2002-08-29
IPC分类号： G05F110
CPC分类号： G05F3/205
摘要： Biasing circuitry for generating and maintaining a substantially constant output bias current. Ratios of selected bias currents and selected transistor sizes ensure that a nominal load current is maintained notwithstanding variations in circuit fabrication processes, power supply voltage and operating temperature.
摘要翻译： 用于产生和维持基本恒定的输出偏置电流的偏置电路。 所选择的偏置电流和所选择的晶体管尺寸的比例确保了电路制造过程，电源电压和工作温度的变化，维持标称负载电流。
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公开(公告)号：US08710865B2
公开(公告)日：2014-04-29
申请号：US13281438
申请日：2011-10-26
IPC分类号： H03K19/173
CPC分类号： H03K19/177
摘要： A field-programmable analog array (FPAA) includes a digital signal routing network, an analog signal routing network, switch elements to interconnect the digital signal routing network with the analog signal routing network, and a configurable analog block (CAB) connected to the analog signal routing network and having a programmable resistor array. The switch elements are implemented via digital memristors, the programmable resistor array is implemented via analog memristors, and/or antifuses within one or more of the digital signal routing network and the analog signal routing network are implemented via digital memristors.
摘要翻译： 现场可编程模拟阵列（FPAA）包括数字信号路由网络，模拟信号路由网络，将数字信号路由网络与模拟信号路由网络互连的开关元件，以及连接到模拟信号的可配置模拟块（CAB） 信号路由网络并具有可编程电阻器阵列。 开关元件通过数字忆阻器实现，可编程电阻器阵列通过模拟忆阻器实现，并且/或数字信号路由网络和模拟信号路由网络内的反熔丝通过数字忆阻器来实现。
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9.发明授权Programmable current-limited voltage buffer, integrated-circuit device and method for current-limiting a memory element 有权可编程限流电压缓冲器，用于限流存储器元件的集成电路器件和方法公开(公告)号：US08681579B2
公开(公告)日：2014-03-25
申请号：US13384885
申请日：2010-04-30
IPC分类号： G11C8/00
CPC分类号： G11C7/12 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0028 , G11C13/0069 , G11C27/005 , G11C27/024 , G11C2013/0073 , G11C2013/0078
摘要： A programmable current-limited voltage buffer. The programmable current-limited voltage buffer includes at least one current-bias circuit, an inverter, a write-current set control circuit, and an adaptive current limiter. The inverter is coupled to the current-bias circuit and a reference-voltage source, and is configured to couple a row line to either the current-bias circuit, or the reference-voltage source, in response to an input signal. The adaptive current limiter is coupled to the current-bias circuit and to the write-current set control circuit, and is configured to limit current flowing through the memory element in a write operation. An integrated circuit device is also provided, along with a method for current limiting a memory element during switching in an array of memory elements.
摘要翻译： 可编程限流电压缓冲器。 可编程限流电压缓冲器包括至少一个电流偏置电路，反相器，写入电流控制电路和自适应限流器。 反相器耦合到电流偏置电路和参考电压源，并且被配置为响应于输入信号将行线耦合到电流偏置电路或参考电压源。 自适应限流器耦合到电流偏置电路和写入电流设置控制电路，并且被配置为在写入操作中限制流过存储器元件的电流。 还提供了一种集成电路器件，以及用于在切换存储元件阵列期间电流限制存储器元件的方法。
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公开(公告)号：US08331129B2
公开(公告)日：2012-12-11
申请号：US12875423
申请日：2010-09-03
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C8/08 , G11C11/5685 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0066 , G11C2013/0076 , G11C2211/5624 , G11C2213/77
摘要： A memory array with write feedback includes a number of row lines intersecting a number of column lines, a memory element connected between one of the row lines and one of the column lines, an electrical condition supply to be selectively applied to one of the row lines; and a feedback control loop to control an electrical condition supplied by the electrical condition supply. A method for setting the state of a memory element within a memory array includes applying an electrical condition to the memory element within the memory array, sensing a resistive state of the memory element, and controlling the electrical condition based on the sensed resistive state to cause the memory element to reach a target resistance.
摘要翻译： 具有写入反馈的存储器阵列包括与多条列线相交的许多行线，连接在行线之一和列线之一之间的存储元件，选择性地施加到行线之一的电气供应 ; 以及用于控制由电气供应提供的电气状况的反馈控制回路。 用于设置存储器阵列内的存储元件的状态的方法包括将电气条件施加到存储器阵列内的存储元件，感测存储元件的电阻状态，以及基于感测到的电阻状态来控制电气状态，从而导致 记忆元件达到目标电阻。
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