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公开(公告)号：US07590392B2
公开(公告)日：2009-09-15
申请号：US11263791
申请日：2005-10-31
申请人： Navindra Navaratnam , Aninda K. Roy
发明人： Navindra Navaratnam , Aninda K. Roy
CPC分类号： H04B3/46
摘要： In some embodiments, a chip with a transmitter having a transmitter driver is provided. Also provided is a general compensation circuit coupled to the transmitter to generally compensate the transmitter driver and a specific compensation circuit coupled to the transmitter driver to specifically compensate the transmitter driver. Other embodiments are disclosed and claimed herein.
摘要翻译： 在一些实施例中，提供具有发射机的具有发射机驱动器的芯片。 还提供了耦合到发射器的通用补偿电路，以大体上补偿发射器驱动器和耦合到发射器驱动器的特定补偿电路，以特别地补偿发射器驱动器。 本文公开和要求保护的其它实施例。
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公开(公告)号：US07429881B2
公开(公告)日：2008-09-30
申请号：US11326952
申请日：2006-01-06
申请人： Chaodan Deng , Songmin Kim , Navindra Navaratnam
发明人： Chaodan Deng , Songmin Kim , Navindra Navaratnam
IPC分类号： G11C7/00
CPC分类号： H03F3/45183 , G11C7/02 , G11C7/062 , H03F3/45475 , H03F3/45632 , H03F2200/279 , H03F2200/471
摘要： According to embodiments of the subject matter disclosed in this application, a wide input common mode sense amplifier may include a level shifter stage and an amplifier stage. The level shifter comprises a CMOS differential amplifier that has a rail-to-rail input common mode range. The level shifter accepts two input signals with a common mode voltage in a rail-to-rail range and produces two output signals with a stable common mode voltage. The differential amplifier amplifies the two output signals from the level shifter stage with high gain. The disclosed sense amplifier may be used to measure delay between two discrete time events.
摘要翻译： 根据本申请中公开的主题的实施例，宽输入共模感测放大器可以包括电平移位器级和放大级。 电平移位器包括具有轨到轨输入共模范围的CMOS差分放大器。 电平转换器接收两个输入信号，其中共轨模式电压为轨至轨范围，并产生两个具有稳定共模电压的输出信号。 差分放大器以高增益放大来自电平移位器级的两个输出信号。 所公开的读出放大器可用于测量两个离散时间事件之间的延迟。
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3.发明申请Wide input common mode sense amplifier and its application as an apparatus to accurately measure delay between two discrete time events 有权宽输入共模感测放大器及其应用作为准确测量两个离散时间事件之间的延迟的装置公开(公告)号：US20070159215A1
公开(公告)日：2007-07-12
申请号：US11326952
申请日：2006-01-06
申请人： Chaodan Deng , Songmin Kim , Navindra Navaratnam
发明人： Chaodan Deng , Songmin Kim , Navindra Navaratnam
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , G11C7/02 , G11C7/062 , H03F3/45475 , H03F3/45632 , H03F2200/279 , H03F2200/471
摘要： According to embodiments of the subject matter disclosed in this application, a wide input common mode sense amplifier may include a level shifter stage and an amplifier stage. The level shifter comprises a CMOS differential amplifier that has a rail-to-rail input common mode range. The level shifter accepts two input signals with a common mode voltage in a rail-to-rail range and produces two output signals with a stable common mode voltage. The differential amplifier amplifies the two output signals from the level shifter stage with high gain. The disclosed sense amplifier may be used to measure delay between two discrete time events.
摘要翻译： 根据本申请中公开的主题的实施例，宽输入共模感测放大器可以包括电平移位器级和放大级。 电平移位器包括具有轨到轨输入共模范围的CMOS差分放大器。 电平转换器接收两个输入信号，其中共轨模式电压为轨至轨范围，并产生两个具有稳定共模电压的输出信号。 差分放大器以高增益放大来自电平移位器级的两个输出信号。 所公开的读出放大器可用于测量两个离散时间事件之间的延迟。
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公开(公告)号：US20140140146A1
公开(公告)日：2014-05-22
申请号：US13680604
申请日：2012-11-19
CPC分类号： G05F1/10 , G11C5/145 , G11C5/147 , G11C11/4074 , G11C2207/105 , H02M3/07 , H02M2003/1566
摘要： Circuitry to provide a supply voltage. A voltage regulator is coupled to receive a target reference signal. The voltage regulator generates a supply voltage (Vtt) and is coupled to receive the supply voltage as an input signal. An upper limit comparator receives an upper limit voltage signal that is higher than the target reference voltage signal and the supply voltage to generate a “too high” signal when the supply voltage exceeds an upper threshold. A lower limit comparator receives a lower limit voltage signal that is lower than the target reference voltage signal and the supply voltage to generate a “too low” signal when the supply voltage is below a lower threshold. A pull up current source is coupled to pull the supply voltage up in response to the too low signal. A pull down current source is coupled to pull the supply voltage down in response to the too high signal.
摘要翻译： 电路提供电源电压。 电压调节器被耦合以接收目标参考信号。 电压调节器产生电源电压（Vtt）并被耦合以接收电源电压作为输入信号。 当电源电压超过上限阈值时，上限比较器接收高于目标参考电压信号和电源电压的上限电压信号，以产生“过高”信号。 下限比较器接收低于目标参考电压信号的下限电压信号和电源电压，以在电源电压低于下阈值时产生“太低”信号。 耦合上拉电流源以响应于太低的信号将电源电压拉高。 耦合下拉电流源以响应于太高的信号而拉低电源电压。
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公开(公告)号：US20090248945A1
公开(公告)日：2009-10-01
申请号：US12059158
申请日：2008-03-31
CPC分类号： G06F13/4077 , H04L25/0272
摘要： In some embodiments, a circuit is provided with a transmitter to generate switching noise during clock events when no transition occurs to reduce data dependent switching noise.
摘要翻译： 在一些实施例中，电路设置有发射机，以便在不发生跳变的时钟事件期间产生开关噪声，以减少依赖于数据的开关噪声。
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公开(公告)号：US20070099572A1
公开(公告)日：2007-05-03
申请号：US11263791
申请日：2005-10-31
申请人： Navindra Navaratnam , Aninda Roy
发明人： Navindra Navaratnam , Aninda Roy
CPC分类号： H04B3/46
摘要： In some embodiments, a chip with a transmitter having a transmitter driver is provided. Also provided is a general compensation circuit coupled to the transmitter to generally compensate the transmitter driver and a specific compensation circuit coupled to the transmitter driver to specifically compensate the transmitter driver. Other embodiments are disclosed and claimed herein.
摘要翻译： 在一些实施例中，提供具有发射机的具有发射机驱动器的芯片。 还提供了耦合到发射器的通用补偿电路，以大体上补偿发射器驱动器和耦合到发射器驱动器的特定补偿电路，以特别地补偿发射器驱动器。 本文公开和要求保护的其它实施例。
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公开(公告)号：US07038513B2
公开(公告)日：2006-05-02
申请号：US10878033
申请日：2004-06-29
IPC分类号： H03K5/12
CPC分类号： H03K19/00323 , H03K5/023 , H03K2005/00136 , H03L7/0812 , H04L25/0288
摘要： A system and method for processing signals determines rise and fall times of a driving signal, compares the rise and fall times to desired values, and independently controls the rise and fall times to equal the desired values. The rise and fall times may be controlled by generating one or more first correction bits based on a difference between the rise time and a corresponding one of the desired values, generating one or more second correction bits based on a difference between the fall time and a corresponding one of the desired values, and then separately applying the bits to independently control the rise and fall times of the driving signal. The driving signal may be an I/O signal or another type of signal.
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8.发明申请公开(公告)号：US20050285648A1
公开(公告)日：2005-12-29
申请号：US10878033
申请日：2004-06-29
CPC分类号： H03K19/00323 , H03K5/023 , H03K2005/00136 , H03L7/0812 , H04L25/0288
摘要： A system and method for processing signals determines rise and fall times of a driving signal, compares the rise and fall times to desired values, and independently controls the rise and fall times to equal the desired values. The rise and fall times may be controlled by generating one or more first correction bits based on a difference between the rise time and a corresponding one of the desired values, generating one or more second correction bits based on a difference between the fall time and a corresponding one of the desired values, and then separately applying the bits to independently control the rise and fall times of the driving signal. The driving signal may be an I/O signal or another type of signal.
摘要翻译： 用于处理信号的系统和方法确定驱动信号的上升和下降时间，将上升和下降时间与期望值进行比较，并且独立地将上升和下降时间控制为等于期望值。 上升和下降时间可以通过基于上升时间和所需值之间的差异产生一个或多个第一校正位来控制，基于下降时间和下降时间之间的差产生一个或多个第二校正位 对应一个期望值，然后分别施加位以独立地控制驱动信号的上升和下降时间。 驱动信号可以是I / O信号或其他类型的信号。
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