公开(公告)号：US20110198710A1

公开(公告)日：2011-08-18

申请号：US13039811

申请日：2011-03-03

Applicant: Jong-Ho LEE ,  Nae-In LEE

Inventor： Jong-Ho LEE ,  Nae-In LEE

IPC: H01L29/772 ,  H01L29/06

CPC classification number: H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7881 ,  H01L29/94

Abstract: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.

Abstract translation: 半导体器件包括硅酸盐界面层和覆盖硅酸盐界面层的高k电介质层。 高k电介质层包括金属合金氧化物。

公开(公告)号：US20080185631A1

公开(公告)日：2008-08-07

申请号：US12098373

申请日：2008-04-04

Applicant: Jong-Ho LEE ,  Nae-In LEE

Inventor： Jong-Ho LEE ,  Nae-In LEE

IPC: H01L29/788 ,  H01L23/58 ,  H01L29/78 ,  H01L29/92

CPC classification number: H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7881 ,  H01L29/94

Abstract: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.

Abstract translation: 半导体器件包括硅酸盐界面层和覆盖硅酸盐界面层的高k电介质层。 高k电介质层包括金属合金氧化物。

公开(公告)号：US20150287682A1

公开(公告)日：2015-10-08

申请号：US14637640

申请日：2015-03-04

Applicant: Sang Hoon AHN ,  Sangho RHA ,  Jongmin BAEK ,  Wookyung YOU ,  Nae-In LEE

Inventor： Sang Hoon AHN ,  Sangho RHA ,  Jongmin BAEK ,  Wookyung YOU ,  Nae-In LEE

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first conductive pattern on a substrate, an insulating diffusion barrier layer conformally covering a surface of the first conductive pattern, the insulation diffusion barrier layer exposed by an air gap region adjacent to a sidewall of the first conductive pattern, and a second conductive pattern on the first conductive pattern, the second conductive pattern penetrating the insulating diffusion barrier layer so as to be in contact with the first conductive pattern.

Abstract translation: 半导体器件包括：衬底上的第一导电图案，保形地覆盖第一导电图案的表面的绝缘扩散阻挡层，由邻近第一导电图案的侧壁的气隙区域暴露的绝缘扩散阻挡层，以及 第二导电图案在第一导电图案上，第二导电图案穿透绝缘扩散阻挡层，以便与第一导电图案接触。

公开(公告)号：US20160329242A1

公开(公告)日：2016-11-10

申请号：US15048993

申请日：2016-02-19

Applicant: Thomas OSZINDA ,  Tae-Jin YIM ,  Sang-Hoon AHN ,  Nae-In LEE

Inventor： Thomas OSZINDA ,  Tae-Jin YIM ,  Sang-Hoon AHN ,  Nae-In LEE

IPC: H01L21/768

CPC classification number: H01L21/76831 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2221/1047

Abstract: In a method of forming a wiring structure, an insulating interlayer is formed on a substrate. The insulating interlayer includes an opening and has pores distributed therein and exposed at a surface thereof. The insulating interlayer is exposed to a silane compound to form a pore sealing layer on the surface of the insulating interlayer and a sidewall of the opening. A conductive pattern filling the opening is formed on the pore sealing layer.

Abstract translation: 在形成布线结构的方法中，在基板上形成绝缘中间层。 绝缘中间层包括开口，并且其中分布有孔并在其表面露出。 将绝缘中间层暴露于硅烷化合物以在绝缘中间层的表面和开口的侧壁上形成孔密封层。 填充开口的导电图案形成在孔密封层上。

公开(公告)号：US20160064565A1

公开(公告)日：2016-03-03

申请号：US14938172

申请日：2015-11-11

Applicant: Dong-Suk SHIN ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM ,  Nae-In LEE

Inventor： Dong-Suk SHIN ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM ,  Nae-In LEE

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L27/088 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

公开(公告)号：US20150214329A1

公开(公告)日：2015-07-30

申请号：US14680349

申请日：2015-04-07

Applicant: Dong-Suk SHIN ,  Hyun-Chul KANG ,  Dong-Hyun ROH ,  Pan-Kwi PARK ,  Geo-Myung SHIN ,  Nae-In LEE ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM

Inventor： Dong-Suk SHIN ,  Hyun-Chul KANG ,  Dong-Hyun ROH ,  Pan-Kwi PARK ,  Geo-Myung SHIN ,  Nae-In LEE ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM

IPC: H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

Abstract translation: 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成沟槽，并且沟槽可以包括有源区的切口部分。 所述方法还可以包括在沟槽中形成嵌入的应力源。 嵌入式应力器可以包括下半导体层和上半导体层，其宽度比下半导体层的宽度窄。 上半导体层的一侧可以不与下半导体层的一侧对准，并且上半导体层的最上表面可以高于有源区的最上表面。