公开(公告)号：US20110198710A1

公开(公告)日：2011-08-18

申请号：US13039811

申请日：2011-03-03

Applicant: Jong-Ho LEE ,  Nae-In LEE

Inventor： Jong-Ho LEE ,  Nae-In LEE

IPC: H01L29/772 ,  H01L29/06

CPC classification number: H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7881 ,  H01L29/94

Abstract: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.

Abstract translation: 半导体器件包括硅酸盐界面层和覆盖硅酸盐界面层的高k电介质层。 高k电介质层包括金属合金氧化物。

公开(公告)号：US20130084713A1

公开(公告)日：2013-04-04

申请号：US13661748

申请日：2012-10-26

Applicant: Jong-Ho LEE ,  Nae-In Lee

Inventor： Jong-Ho LEE ,  Nae-In Lee

IPC: H01L21/02

CPC classification number: H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7881 ,  H01L29/94

Abstract: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.

Abstract translation: 半导体器件包括硅酸盐界面层和覆盖硅酸盐界面层的高k电介质层。 高k电介质层包括金属合金氧化物。

公开(公告)号：US20080185631A1

公开(公告)日：2008-08-07

申请号：US12098373

申请日：2008-04-04

Applicant: Jong-Ho LEE ,  Nae-In LEE

Inventor： Jong-Ho LEE ,  Nae-In LEE

IPC: H01L29/788 ,  H01L23/58 ,  H01L29/78 ,  H01L29/92

CPC classification number: H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7881 ,  H01L29/94

Abstract: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.

Abstract translation: 半导体器件包括硅酸盐界面层和覆盖硅酸盐界面层的高k电介质层。 高k电介质层包括金属合金氧化物。

公开(公告)号：US20090322714A1

公开(公告)日：2009-12-31

申请号：US12487198

申请日：2009-06-18

Applicant: Kwang-Kee LEE ,  Jong-Ho LEE ,  Sung-Wook BYUN ,  Un-Gyo JUNG ,  Glenn A. ADAMS

Inventor： Kwang-Kee LEE ,  Jong-Ho LEE ,  Sung-Wook BYUN ,  Un-Gyo JUNG ,  Glenn A. ADAMS

IPC: G09G5/00

CPC classification number: H04N5/45 ,  H04N21/4316 ,  H04N21/43615 ,  H04N21/4433 ,  H04N21/4622

Abstract: The present invention performs multiscreen configuration and multiscreen management by using a plurality of screens and a plurality of methods in order to represent a plurality of service contents. In accordance with a multiscreen configuration method of the present invention, by mutually assigning one or more broadcasting services, one or more logical screens, one or more display screens, and one or more output ports, ultimately outputting service contents which are executed on screens assigned by output ports, and setting, changing, and reporting configuration of a multiscreen, the configuration of the multiscreen may be set or reset so as to effectively output various service contents on the multiscreen by using a desired method.

Abstract translation: 本发明通过使用多个屏幕和多种方法来执行多屏幕配置和多屏幕管理，以便表示多个服务内容。 根据本发明的多屏配置方法，通过相互分配一个或多个广播服务，一个或多个逻辑屏幕，一个或多个显示屏幕和一个或多个输出端口，最终输出在分配的屏幕上执行的服务内容 通过输出端口以及多屏幕的设置，改变和报告配置，可以设置或重置多画面的配置，以便通过使用期望的方法在多画面上有效地输出各种服务内容。

公开(公告)号：US20090045513A1

公开(公告)日：2009-02-19

申请号：US12193561

申请日：2008-08-18

Applicant: Pyoung-Wan KIM ,  Eun-Chul AHN ,  Jong-Ho LEE ,  Teak-Hoon LEE ,  Chul-Yong JANG

Inventor： Pyoung-Wan KIM ,  Eun-Chul AHN ,  Jong-Ho LEE ,  Teak-Hoon LEE ,  Chul-Yong JANG

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L23/49816 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor chip package including a semiconductor chip including a first surface having bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; redistribution patterns extending from the bonding pads over the molding extension part, and electrically connected to the bonding pads; bump solder balls on the redistribution patterns; and a molding layer configured to cover the first surface of the semiconductor chip and the molding extension part, while exposing portions of each of the bump solder balls. The molding layer has concave meniscus surfaces between the bump solder balls adjacent to each other.

Abstract translation: 一种包括半导体芯片的半导体芯片封装，所述半导体芯片包括具有接合焊盘的第一表面，与所述第一表面相对的第二表面和侧壁; 围绕半导体芯片的第二表面和侧壁的成型延伸部分; 重新分布图案从接合焊盘延伸到模制延伸部分上，并且电连接到焊盘; 碰撞焊球上的再分布图案; 以及模制层，其被配置为覆盖半导体芯片的第一表面和模制延伸部分，同时暴露每个凸块焊球的部分。 成型层在彼此相邻的凸块焊料球之间具有凹面弯月面。

公开(公告)号：US20100207180A1

公开(公告)日：2010-08-19

申请号：US12708342

申请日：2010-02-18

Applicant: Jong-Ho LEE

Inventor： Jong-Ho LEE

IPC: H01L27/108

CPC classification number: H01L29/7841 ,  H01L27/108 ,  H01L27/10802

Abstract: Provided is a one-transistor (1T) floating-body DRAM cell device including a substrate; a gate stack which is formed on the substrate; a control electrode which is disposed on the substrate and of which some or entire portion is surrounded by the gate stack; a semiconductor layer which is formed on the gate stack; a source and a drain which are formed in the surface of the semiconductor layer and of which lower surfaces are not in contact with the gate stack; a gate insulating layer which is formed on the semiconductor layer; and a gate electrode which is formed on the gate insulating layer, wherein the remaining portion of the semiconductor layer excluding the source and the drain is configured as a floating body. The miniaturization characteristic and performance of a MOS-based DRAM cell device can be improved, and a memory capacity can be increased.

Abstract translation: 提供了一种包括衬底的单晶体管（1T）浮体DRAM单元器件; 形成在基板上的栅极堆叠; 控制电极，其设置在所述基板上，并且其一些或全部部分被所述栅极堆叠包围; 形成在栅叠层上的半导体层; 源极和漏极，其形成在半导体层的表面中并且其下表面不与栅极堆叠接触; 形成在半导体层上的栅极绝缘层; 以及形成在所述栅极绝缘层上的栅极，其中，除了所述源极和漏极之外的所述半导体层的剩余部分被构造为浮体。 可以提高基于MOS的DRAM单元装置的小型化特性和性能，并且可以提高存储容量。

公开(公告)号：US20090309206A1

公开(公告)日：2009-12-17

申请号：US12484491

申请日：2009-06-15

Applicant: Young-Lyong KIM ,  Jong-Ho LEE ,  Cheul-Joong YOUN ,  Eun-Chul AHN

Inventor： Young-Lyong KIM ,  Jong-Ho LEE ,  Cheul-Joong YOUN ,  Eun-Chul AHN

IPC: H01L25/11

CPC classification number: H01L25/105 ,  H01L24/73 ,  H01L24/91 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package includes a first package that a first semiconductor chip is mounted on a front side of a first substrate and a redistributed pad including a first redistributed pad electrically connected to the first substrate and a second redistributed pad electrically connected to the first redistributed pad is disposed on the first semiconductor chip and a second package that a second semiconductor chip is mounted on a front side of a second substrate, the second package including a connection member electrically connected to the second redistributed pad. The connection member electrically connected to the redistributed pad electrically connects the first and second packages to each other.

Abstract translation: 半导体封装以及半导体封装的制造方法。 半导体封装包括第一封装，第一半导体芯片安装在第一基板的前侧，以及重新分布的焊盘，其包括电连接到第一基板的第一再分布焊盘和电连接到第一再分布焊盘的第二再分布焊盘 设置在第一半导体芯片上的第二封装以及第二半导体芯片安装在第二基板的正面上的第二封装，所述第二封装包括与第二再分布焊盘电连接的连接部件。 电连接到再分布垫的连接构件将第一和第二封装彼此电连接。

公开(公告)号：US20080265432A1

公开(公告)日：2008-10-30

申请号：US12113009

申请日：2008-04-30

Applicant: Min-Ho O ,  Eun-Chul AHN ,  Jong-Ho LEE ,  Pyoung-Wan KIM ,  Hyeon HWANG ,  Teak-Hoon LEE

Inventor： Min-Ho O ,  Eun-Chul AHN ,  Jong-Ho LEE ,  Pyoung-Wan KIM ,  Hyeon HWANG ,  Teak-Hoon LEE

IPC: H01L23/49

CPC classification number: H01L24/85 ,  H01L23/3121 ,  H01L23/562 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/27013 ,  H01L2224/29007 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32506 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83051 ,  H01L2224/83101 ,  H01L2224/83194 ,  H01L2224/83801 ,  H01L2224/85181 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

Abstract: A multi-chip package includes a mounting substrate, a first semiconductor chip, a second semiconductor chip, a reinforcing member, conductive wires and an encapsulant. The first semiconductor chip is disposed on the mounting substrate. The second semiconductor chip is disposed on the first semiconductor chip. An end portion of the second semiconductor chip protrudes from a side portion of the first semiconductor chip. A reinforcing member is disposed on an overlapping region of the second semiconductor chip where the second semiconductor chip overlaps with the side portion of the first semiconductor chip such that the reinforcing member decreases downward bending of the second semiconductor chip from the side portion of the first semiconductor chip. The conductive wires electrically connect the first and second semiconductor chips to the mounting substrate. The encapsulant is disposed on the mounting substrate to cover the first and second semiconductor chips and the conductive wires.

Abstract translation: 多芯片封装包括安装基板，第一半导体芯片，第二半导体芯片，加强构件，导线和密封剂。 第一半导体芯片设置在安装基板上。 第二半导体芯片设置在第一半导体芯片上。 第二半导体芯片的端部从第一半导体芯片的侧部突出。 加强构件设置在第二半导体芯片的重叠区域上，其中第二半导体芯片与第一半导体芯片的侧部重叠，使得加强构件从第一半导体的侧部减小第二半导体芯片的向下弯曲 芯片。 导线将第一和第二半导体芯片电连接到安装基板。 密封剂设置在安装基板上以覆盖第一和第二半导体芯片和导线。

公开(公告)号：US20080017930A1

公开(公告)日：2008-01-24

申请号：US11862404

申请日：2007-09-27

Applicant: Min-Joo KIM ,  Hyung-Suk JUNG ,  Jong-Ho LEE ,  Sungkee HAN

Inventor： Min-Joo KIM ,  Hyung-Suk JUNG ,  Jong-Ho LEE ,  Sungkee HAN

IPC: H01L29/78

CPC classification number: H01L21/823842 ,  H01L21/265 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor device and related methods of manufacture are disclosed in which dual work function metal gate electrodes are formed from a single metal layer by doping the metal layer with carbon and/or fluorine.

Abstract translation: 公开了一种半导体器件及相关的制造方法，其中通过用碳和/或氟掺杂金属层，由单一金属层形成双功能金属栅电极。

公开(公告)号：US20160315087A1

公开(公告)日：2016-10-27

申请号：US15069920

申请日：2016-03-14

Applicant: Wei-Hsiung TSENG ,  Ju-Youn KIM ,  Seok-Jun WON ,  Jong-Ho LEE ,  Hye-Lan LEE ,  Yong-Ho HA

Inventor： Wei-Hsiung TSENG ,  Ju-Youn KIM ,  Seok-Jun WON ,  Jong-Ho LEE ,  Hye-Lan LEE ,  Yong-Ho HA

IPC: H01L27/092 ,  H01L29/43 ,  H01L29/49

CPC classification number: H01L27/0924 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/845 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/435 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848

Abstract: Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench; forming a high-k dielectric layer in the first trench; successively forming a diffusion layer and a blocking layer on the high-k dielectric layer; subsequently performing annealing; after the annealing, successively removing the blocking layer and the diffusion layer; forming a first barrier layer on the high-k dielectric layer; successively forming a work function adjustment layer and a gate conductor on the first barrier layer; and forming a capping layer on the gate conductor.