公开(公告)号：US20130307151A1

公开(公告)日：2013-11-21

申请号：US13472555

申请日：2012-05-16

申请人： Griselda Bonilla ,  Junjing Bao ,  Samuel S. Choi ,  Ronald G. Filippi ,  Naftali E. Lustig ,  Andrew H. Simon

发明人： Griselda Bonilla ,  Junjing Bao ,  Samuel S. Choi ,  Ronald G. Filippi ,  Naftali E. Lustig ,  Andrew H. Simon

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76849 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of repairing hollow metal void defects in interconnects and resulting structures. After polishing interconnects, hollow metal void defects become visible. The locations of the defects are largely predictable. A repair method patterns a mask material to have openings over the interconnects (and, sometimes, the adjacent dielectric layer) where defects are likely to appear. A local metal cap is formed in the mask openings to repair the defect. A dielectric cap covers the local metal cap and any recesses formed in the adjacent dielectric layer.

摘要翻译： 一种在互连和结构中修复空心金属空隙缺陷的方法。 抛光互连后，中空金属空隙缺陷变得可见。 缺陷的位置在很大程度上是可预测的。 修复方法将掩模材料图案化成可能出现缺陷的互连（以及有时相邻的介电层）上的开口。 在掩模孔中形成局部金属盖，以修复缺陷。 电介质盖覆盖局部金属盖和形成在相邻电介质层中的任何凹陷。

公开(公告)号：US20120249159A1

公开(公告)日：2012-10-04

申请号：US13074407

申请日：2011-03-29

申请人： Ronald G. Filippi ,  Griselda Bonilla ,  Kaushik Chanda ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

发明人： Ronald G. Filippi ,  Griselda Bonilla ,  Kaushik Chanda ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

IPC分类号： G01R31/04 ,  G01R31/02 ,  H01L23/62

CPC分类号： H01L23/5226 ,  G01R31/025 ,  G01R31/04 ,  G01R31/07 ,  G01R31/327 ,  H01L23/5256 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53295 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/00

摘要： A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.

摘要翻译： 线路的后端（BEOL）保险丝结构具有一叠通孔。 通孔的堆叠导致高的纵横比，使得通孔内的衬里和种子覆盖较差。 衬里和种子层的弱点导致电迁移（EM）故障的较高概率。 保险丝结构由于衬垫和种子覆盖不良而解决故障。 设计特征允许确定故障发生的位置，确定熔丝编程之后受损区域的程度，并防止损坏的介质区域的进一步传播。

公开(公告)号：US20110175226A1

公开(公告)日：2011-07-21

申请号：US12691213

申请日：2010-01-21

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Chao-Kun Hu ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Stephan Grunow ,  Chao-Kun Hu ,  Naftali E. Lustig ,  Andrew H. Simon ,  Ping-Chuan Wang

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76846 ,  H01L21/76847 ,  H01L23/522 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure for an integrated circuit (IC) device includes a metal line formed within a dielectric layer, the metal line having one or more vertical diffusion barriers therein; wherein the one or more vertical diffusion barriers correspond to a liner material of a via formed above the metal line, with the via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line

摘要翻译： 用于集成电路（IC）器件的互连结构包括形成在电介质层内的金属线，所述金属线在其中具有一个或多个垂直扩散阻挡层; 其中所述一个或多个垂直扩散屏障对应于在所述金属线上方形成的通孔的衬垫材料，所述通孔完全延伸穿过所述金属线的厚度，使得所述通孔的最底部包括所述金属线的一部分

公开(公告)号：US09685404B2

公开(公告)日：2017-06-20

申请号：US13348011

申请日：2012-01-11

申请人： Junjing Bao ,  Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Dan Moy ,  Andrew H. Simon

发明人： Junjing Bao ,  Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Dan Moy ,  Andrew H. Simon

IPC分类号： H01L21/768 ,  H01L23/525 ,  H01L23/522 ,  H01H85/02

CPC分类号： H01L23/5256 ,  H01H2085/0275 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.

公开(公告)号：US09059169B2

公开(公告)日：2015-06-16

申请号：US13165087

申请日：2011-06-21

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald G. Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald G. Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon

IPC分类号： H01L21/26 ,  H01L23/525 ,  H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5256 ,  H01L21/768 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure.

摘要翻译： 提供线后端的电熔丝结构（BEOL）互连和制造方法。 该方法包括在衬底中与第一底层金属线对齐形成互连通孔，并在衬底中形成电熔丝通孔，露出第二下面的金属线。 该方法还包括用第二底层金属线形成缺陷并用金属填充互连通孔并与第一底层金属线接触，从而形成互连结构。 该方法还包括用金属填充e熔丝通孔并与缺陷和第二下面的金属线接触，从而形成电熔丝结构。

公开(公告)号：US20120146224A1

公开(公告)日：2012-06-14

申请号：US13362292

申请日：2012-01-31

申请人： Junjing Bao ,  Tien-Jen J. Cheng ,  Naftali E. Lustig

发明人： Junjing Bao ,  Tien-Jen J. Cheng ,  Naftali E. Lustig

IPC分类号： H01L23/538

CPC分类号： H01L21/76829 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/96 ,  H01L2924/00

摘要： In a BEOL process, UV radiation is used in a curing process of ultra low-k (ULK) dielectrics. This radiation penetrates through the ULK material and reaches the cap film underneath it. The interaction between the UV light and the film leads to a change the properties of the cap film. Of particular concern is the change in the stress state of the cap from compressive to tensile stress. This leads to a weaker dielectric-cap interface and mechanical failure of the ULK film. A layer of nanoparticles is inserted between the cap and the ULK film. The nanoparticles absorb the UV light before it can damage the cap film, thus maintaining the mechanical integrity of the ULK dielectric.

摘要翻译： 在BEOL工艺中，UV辐射用于超低k（ULK）电介质的固化过程中。 该辐射穿过ULK材料并到达其下方的盖膜。 UV光和膜之间的相互作用导致盖膜的性质的改变。 特别令人关切的是，帽的应力状态从压缩到拉伸应力的变化。 这导致ULK膜的介电盖接口和机械故障较弱。 将一层纳米颗粒插入盖和ULK膜之间。 纳米粒子吸收紫外线，然后才能损坏盖膜，从而保持ULK电介质的机械完整性。

公开(公告)号：US5337015A

公开(公告)日：1994-08-09

申请号：US75628

申请日：1993-06-14

申请人： Naftali E. Lustig ,  Randall M. Feenstra ,  William L. Guthrie

发明人： Naftali E. Lustig ,  Randall M. Feenstra ,  William L. Guthrie

IPC分类号： B24B37/013 ,  G01B7/34 ,  G01D5/24 ,  G01R27/26

CPC分类号： B24B37/013 ,  G01B7/345 ,  G01D5/2405

摘要： An in-situ thickness monitoring/endpoint detection method and apparatus for chemical-mechanical polishing (CMP) of a dielectric layer on a top surface of a semiconductor wafer is disclosed. The apparatus comprises center and guard electrodes and associated electronic circuitry, including a high frequency, low voltage signal generating means, for converting a current which is inversely proportional to the dielectric layer thickness into a corresponding analog voltage. A position detection device triggers an analog-to-digital converter to convert the analog voltage into a digital signal while the wafer is located within a detection region as the wafer is being polished. A control means gathers the digital signals corresponding to the thickness data for processing and CMP device control.

摘要翻译： 公开了一种在半导体晶片的顶表面上的电介质层的用于化学机械抛光（CMP）的原位厚度监测/终点检测方法和装置。 该装置包括中心和保护电极以及相关联的电子电路，包括用于将与电介质层厚度成反比的电流​​转换成对应的模拟电压的高频低电压信号发生装置。 当晶片被抛光时，位置检测装置触发模数转换器将模拟电压转换为数字信号，同时晶片位于检测区域内。 控制装置收集与用于处理的厚度数据相对应的数字信号和CMP装置控制。

公开(公告)号：US08962467B2

公开(公告)日：2015-02-24

申请号：US13399266

申请日：2012-02-17

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald G. Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon ,  Junjing Bao

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald G. Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Andrew H. Simon ,  Junjing Bao

IPC分类号： H01L21/44

CPC分类号： H01L23/5256 ,  H01H69/02 ,  H01H85/046 ,  H01H2085/0275 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  Y10T29/49107 ,  H01L2924/00

摘要： Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps.

摘要翻译： 提供更可靠的保险丝熔断位置的结构及其制作方法。 在熔断器熔断之前，垂直金属保险丝熔断结构在熔丝导体有意损坏的部分。 损坏的部分有助于熔断器在已知位置中熔断，从而降低后吹回路中的电阻变化。 同时，在保险丝熔断之前，保险丝结构能够正常工作。 熔丝导体的损坏部分是通过在保险丝导体的一部分上方的盖层中形成开口，并蚀刻熔丝导体而制成的。 优选地，开口对准，使得损坏部分在熔丝导体的顶角上。 可以在与损坏的保险丝导体相邻的绝缘体中形成空腔。 具有空腔的损坏的保险丝结构可以容易地结合在制造具有气隙的集成电路的过程中。

公开(公告)号：US20130176073A1

公开(公告)日：2013-07-11

申请号：US13348011

申请日：2012-01-11

申请人： Junjing Bao ,  Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Dan Moy ,  Andrew H. Simon

发明人： Junjing Bao ,  Griselda Bonilla ,  Kaushik Chanda ,  Samuel S. Choi ,  Ronald Filippi ,  Stephan Grunow ,  Naftali E. Lustig ,  Dan Moy ,  Andrew H. Simon

IPC分类号： H01H37/76 ,  H01L21/768 ,  B44C1/22 ,  H01L23/525

CPC分类号： H01L23/5256 ,  H01H2085/0275 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.

摘要翻译： 公开了一种BEOL电子熔断器，其可靠地吹入通孔并且甚至可以在最窄的节距BEOL层中形成。 BEOL电子熔断器可以利用线路第一双镶嵌工艺形成，以创建一个亚光刻通孔，作为电子熔丝的可编程链路。 亚光刻通孔可以使用标准光刻图案化，并且通孔的横截面可以被调谐以匹配目标编程电流。

公开(公告)号：US20120068315A1

公开(公告)日：2012-03-22

申请号：US12885596

申请日：2010-09-20

申请人： Junjing Bao ,  Tien-Jen J. Cheng ,  Naftali E. Lustig

发明人： Junjing Bao ,  Tien-Jen J. Cheng ,  Naftali E. Lustig

IPC分类号： H01L23/552 ,  H01L21/768

CPC分类号： H01L21/76829 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/96 ,  H01L2924/00

摘要： In a BEOL process, UV radiation is used in a curing process of ultra low-k (ULK) dielectrics. This radiation penetrates through the ULK material and reaches the cap film underneath it. The interaction between the UV light and the film leads to a change the properties of the cap film. Of particular concern is the change in the stress state of the cap from compressive to tensile stress. This leads to a weaker dielectric-cap interface and mechanical failure of the ULK film. A layer of nanoparticles is inserted between the cap and the ULK film. The nanoparticles absorb the UV light before it can damage the cap film, thus maintaining the mechanical integrity of the ULK dielectric.

摘要翻译： 在BEOL工艺中，UV辐射用于超低k（ULK）电介质的固化过程中。 该辐射穿过ULK材料并到达其下方的盖膜。 UV光和膜之间的相互作用导致盖膜的性质的改变。 特别令人关切的是，帽的应力状态从压缩到拉伸应力的变化。 这导致ULK膜的介电盖接口和机械故障较弱。 将一层纳米颗粒插入盖和ULK膜之间。 纳米粒子吸收紫外线，然后才能损坏盖膜，从而保持ULK电介质的机械完整性。