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    MULTI-PATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    MULTI-PATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE 审中-公开
    多通道可访问的半导体存储器件

    公开(公告)号：US20070150668A1

    公开(公告)日：2007-06-28

    申请号：US11548603

    申请日：2006-10-11

    申请人： Kyoung-Hwan KWON ,  Dong-Il SEO ,  Ho-Cheol LEE ,  Han-Gu SOHN ,  Yun-Hee SHIN

    发明人： Kyoung-Hwan KWON ,  Dong-Il SEO ,  Ho-Cheol LEE ,  Han-Gu SOHN ,  Yun-Hee SHIN

    IPC分类号： G06F12/00

    CPC分类号： G11C7/1075 ,  G06F13/1663 ,  G11C8/10 ,  G11C11/413

    摘要： A semiconductor memory device includes ports, data line pairs, where each port associated with one of the data line pairs, sets of address lines, where each port associated with one of the sets of address lines, a shared memory region of a memory cell array, where the shared memory region accessible through the ports, an access controller coupled to the ports and configured to generate an access selection signal in response to a plurality of control signals received through the ports, and an access router coupled to the shared memory region, the data line pairs, and the sets of address lines, the access router configured to selectively couple one of the sets of address lines and one of the data line pairs to the shared memory region in response to the access selection signal.

    摘要翻译： 半导体存储器件包括端口，数据线对，其中与数据线对之一相关联的每个端口，地址线集合，其中每个端口与地址线中的一组相关联，存储器单元阵列的共享存储器区域 ，其中所述共享存储器区域可通过所述端口访问，访问控制器耦合到所述端口并且被配置为响应于通过所述端口接收的多个控制信号而生成访问选择信号;以及访问路由器，其耦合到所述共享存储器区域， 所述数据线对和所述地址线组，所述接入路由器被配置为响应于所述接入选择信号而选择性地将所述地址线组中的一个和所述数据线对之一耦合到所述共享存储器区域。

    METHOD CONTROLLING DEEP POWER DOWN MODE IN MULTI-PORT SEMICONDUCTOR MEMORY
    5.
    发明申请
    METHOD CONTROLLING DEEP POWER DOWN MODE IN MULTI-PORT SEMICONDUCTOR MEMORY 有权
    在多端口半导体存储器中控制深度掉电模式的方法

    公开(公告)号：US20100309742A1

    公开(公告)日：2010-12-09

    申请号：US12768060

    申请日：2010-04-27

    申请人： Ho-Cheol LEE ,  Jung-Bae LEE

    发明人： Ho-Cheol LEE ,  Jung-Bae LEE

    IPC分类号： G11C5/14 ,  G11C8/16

    CPC分类号： G11C5/148 ,  G11C5/144 ,  G11C5/147 ,  G11C8/16

    摘要： Disclosed is a method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors. Control of the deep power down mode in the multi-port semiconductor memory is performed such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports.

    摘要翻译： 公开了一种在多端口半导体存储器中控制深度掉电模式的方法，该多端口半导体存储器具有连接到多个处理器的多个端口。 执行多端口半导体存储器中的深度掉电模式的控制，使得根据通过多个端口中的各个端口施加的信号来确定深度掉电模式的激活/去激活。

    MULTI PORT MEMORY DEVICE WITH SHARED MEMORY AREA USING LATCH TYPE MEMORY CELLS AND DRIVING METHOD
    6.
    发明申请
    MULTI PORT MEMORY DEVICE WITH SHARED MEMORY AREA USING LATCH TYPE MEMORY CELLS AND DRIVING METHOD 失效
    具有使用锁存型存储器单元的共享存储区域的多端口存储器件和驱动方法

    公开(公告)号：US20090254698A1

    公开(公告)日：2009-10-08

    申请号：US12392432

    申请日：2009-02-25

    申请人： Jin-Hyoung KWON ,  Kyung-Woo NAM ,  Han-Gu SOHN ,  Ho-Cheol LEE ,  Kwang-Myeong JANG

    发明人： Jin-Hyoung KWON ,  Kyung-Woo NAM ,  Han-Gu SOHN ,  Ho-Cheol LEE ,  Kwang-Myeong JANG

    IPC分类号： G06F12/00

    CPC分类号： G11C11/413 ,  G11C7/1075

    摘要： A multiport semiconductor memory device includes; first and second port units respectively coupled to first and second processors, first and second dedicated memory area accessed by first and second processors, respectively and implemented using DRAM cells, a shared memory area commonly accessed by the first and second processors via respective first and second port units and implemented using memory cells different from the DRAM cells implementing the first and second dedicated memory areas, and a port connection control unit controlling data path configuration between the shared memory area and the first and second port units to enable data communication between the first and second processors through the shared memory area.

    摘要翻译： 多端口半导体存储器件包括： 分别耦合到第一和第二处理器的第一和第二端口单元，分别由第一和第二处理器访问的第一和第二专用存储器区域，并且使用DRAM单元实现;第一和第二处理器通过相应的第一和第二处理器共同访问的共享存储器区域 端口单元，并且使用与实现第一和第二专用存储区域的DRAM单元不同的存储器单元来实现，以及端口连接控制单元，其控制共享存储区域与第一和第二端口单元之间的数据路径配置，以使得第一 和第二个处理器通过共享内存区域。

    SELF-REFRESH CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    7.
    发明申请
    SELF-REFRESH CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
    自熔控制电路和包括其的半导体存储器件

    公开(公告)号：US20080205183A1

    公开(公告)日：2008-08-28

    申请号：US12031110

    申请日：2008-02-14

    申请人： Soo-Man HWANG ,  Ho-Cheol LEE

    发明人： Soo-Man HWANG ,  Ho-Cheol LEE

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4087 ,  G11C2211/4065 ,  G11C2211/4068

    摘要： A refresh control circuit in a semiconductor memory device includes a refresh controller, a voltage generator and a word line enable circuit. The refresh period controller generates a control signal in response to a self-refresh signal, the control signal indicating a nominal initiation of a refresh period. The voltage generator generates an output voltage in response to the control signal. The output voltage is boosted from a low voltage to a high voltage during the refresh period. The word line enable circuit generates a word line enable signal in response to the control signal, wherein the word line enable signal is activated following a delay after the nominal initiation of the refresh period, and the delay allows the voltage generator to fully boost the output voltage.

    摘要翻译： 半导体存储器件中的刷新控制电路包括刷新控制器，电压发生器和字线使能电路。 刷新周期控制器响应于自刷新信号产生控制信号，该控制信号指示刷新周期的标称启动。 电压发生器响应于控制信号产生输出电压。 在刷新期间，输出电压从低电压升压到高电压。 字线使能电路响应于控制信号产生字线使能信号，其中在刷新周期的标称启动之后的延迟之后，字线使能信号被激活，并且延迟允许电压发生器完全提升输出 电压。

    STACKED SEMICONDUCTOR DEVICE
    8.
    发明申请
    STACKED SEMICONDUCTOR DEVICE 有权
    堆叠半导体器件

    公开(公告)号：US20110260331A1

    公开(公告)日：2011-10-27

    申请号：US13026460

    申请日：2011-02-14

    申请人： Ho-Cheol LEE

    发明人： Ho-Cheol LEE

    IPC分类号： H01L23/48

    CPC分类号： H01L23/544 ,  H01L24/04 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552

    摘要： Provided is a stacked semiconductor device including n stacked chips. Each chip includes “j” corresponding upper and lower electrodes, wherein j is a minimal natural number greater than or equal to n/2, and an identification code generator including a single inverter connecting one of the j first upper electrode to a corresponding one of the j lower electrodes. The upper electrodes receive a previous identification code, rotate the previous identification code by a unit of 1 bit, and invert 1 bit of the rotated previous identification code to generate a current identification code. The current identification code is applied through the j lower electrodes and corresponding TSVs to communicate the current identification code to the upper adjacent chip.

    摘要翻译： 提供了包括n个堆叠芯片的堆叠半导体器件。 每个芯片包括对应的上部和下部电极的“j”，其中j是大于或等于n / 2的最小自然数，以及识别码发生器，其包括将j个第一上电极中的一个连接到 j个下电极。 上电极接收先前的识别码，以1位为单位旋转先前的识别码，并且反转已转动的先前识别码的1位，以产生当前识别码。 通过j个下部电极和相应的TSV施加当前的识别码，以将当前识别码传送到上部相邻的芯片。

    MULTIPATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE WITH HOST INTERFACE BETWEEN PROCESSORS
    10.
    发明申请
    MULTIPATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE WITH HOST INTERFACE BETWEEN PROCESSORS 有权
    具有处理器之间主机接口的多路可访问半导体存储器件

    公开(公告)号：US20080077937A1

    公开(公告)日：2008-03-27

    申请号：US11829859

    申请日：2007-07-27

    申请人： Yun-Hee SHIN ,  Han-Gu SOHN ,  Young-Min LEE ,  Dong-Hyuk LEE ,  Jong-Wook PARK ,  Ho-Cheol LEE ,  Mi-Jo KIM ,  Jung-Sik KIM ,  Chang-Ho LEE

    发明人： Yun-Hee SHIN ,  Han-Gu SOHN ,  Young-Min LEE ,  Dong-Hyuk LEE ,  Jong-Wook PARK ,  Ho-Cheol LEE ,  Mi-Jo KIM ,  Jung-Sik KIM ,  Chang-Ho LEE

    IPC分类号： G06F15/167 ,  G06F9/30

    CPC分类号： G11C7/1075 ,  G11C7/1012 ,  G11C11/4096

    摘要： A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.

    摘要翻译： 多路可及半导体存储器件提供处理器之间的接口功能。 存储器设备可以包括具有可操作地耦合到两个或更多个端口的共享存储器区域的存储单元阵列，该两个或多个端口可由两个或多个处理器独立地访问;访问路径形成单元，用于在一个端口和共享之间形成数据访问路径 响应于由处理器施加的外部信号的存储区域以及具有信号量区域和由两个或多个处理器在共享存储器区域中可访问的邮箱区域的接口单元，以提供用于两个或多个处理器之间的通信的接口功能。