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    Semiconductor memory device
    1.
    发明申请
    Semiconductor memory device 审中-公开
    半导体存储器件

    公开(公告)号：US20060154417A1

    公开(公告)日：2006-07-13

    申请号：US11330806

    申请日：2006-01-11

    申请人： Naoyuki Shinmura ,  Shigeo Ohnishi ,  Tetsuya Ohnishi ,  Shinobu Yamazaki ,  Takahiro Shibuya ,  Takashi Nakano ,  Masayuki Tajiri

    发明人： Naoyuki Shinmura ,  Shigeo Ohnishi ,  Tetsuya Ohnishi ,  Shinobu Yamazaki ,  Takahiro Shibuya ,  Takashi Nakano ,  Masayuki Tajiri

    IPC分类号： H01L21/8242

    CPC分类号： H01L45/1675 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641

    摘要： The present invention is directed towards a method of manufacturing a semiconductor memory device arranged of a cross point memory array having memory elements provided between upper and lower electrodes for storage of data. The present invention comprises a lower electrode lines forming step of planarizing each of the lower electrode lines and insulating layers provided on both sides of the lower electrode line so as to be substantially uniform in the height thus for patterning the lower electrode lines, a memory element layer depositing step of depositing on the lower electrode lines a memory element layer for the memory elements, and an annealing step of annealing with heat treatment either between the lower electrode lines forming step and the memory element layer depositing step or after the memory element layer depositing step so that any damages caused by the polishing of the surface of the lower electrode lines can be eliminated.

    摘要翻译： 本发明涉及一种制造半导体存储器件的方法，该半导体存储器件被布置成具有设置在上部和下部电极之间的存储元件的交叉点存储器阵列，用于存储数据。 本发明包括下电极线，其形成步骤：将设置在下电极线两侧的每个下电极线和绝缘层平坦化，以使其高度大致均匀，从而构图下电极线;存储元件 在下电极线上沉积用于存储元件的存储元件层的层沉积步骤，以及在下电极线形成步骤和存储元件层沉积步骤之间或在存储元件层沉积之后进行热处理退火的退火步骤 使得可以消除由下电极线的表面的抛光引起的任何损坏。

    Method of forming a device isolation region
    2.
    发明授权
    Method of forming a device isolation region 失效
    形成器件隔离区域的方法

    公开(公告)号：US06187648B1

    公开(公告)日：2001-02-13

    申请号：US09270755

    申请日：1999-03-17

    申请人： Tsukasa Doi ,  Shigeo Ohnishi ,  Katsuji Iguchi ,  Naoyuki Shinmura

    发明人： Tsukasa Doi ,  Shigeo Ohnishi ,  Katsuji Iguchi ,  Naoyuki Shinmura

    IPC分类号： H01L2176

    CPC分类号： H01L21/76224

    摘要： A method of forming a device isolation region includes the steps of: forming a first dielectric film and an oxidation-resistant deposition film successively on a semiconductor substrate; forming a trench groove in the semiconductor substrate by successively processing the oxidation-resistant deposition film, the first dielectric film and the semiconductor substrate by anisotropic etching; forming a second dielectric film to cover at least an inner surface of the trench groove; depositing a third dielectric film in the trench groove so that the thickness of the third dielectric film buried in the trench groove is larger than a depth of the trench groove; planarizing a surface of the third dielectric film and an upper surface of the trench groove; and removing the oxidation-resistant deposition film and the first dielectric film to form the device isolation region, wherein a thermal treatment of the entire substrate is carried out to densify the third dielectric film and to oxidize an interface between the second dielectric film and the semiconductor substrate.

    摘要翻译： 形成器件隔离区域的方法包括以下步骤：在半导体衬底上依次形成第一电介质膜和抗氧化淀积膜; 通过各向异性腐蚀对所述耐氧化沉积膜，所述第一电介质膜和所述半导体衬底进行连续处理，在所述半导体衬底中形成沟槽; 形成第二电介质膜以覆盖所述沟槽的至少内表面; 在沟槽中沉积第三电介质膜，使得埋在沟槽中的第三电介质膜的厚度大于沟槽的深度; 平面化第三电介质膜的表面和沟槽的上表面; 以及去除所述抗氧化沉积膜和所述第一电介质膜以形成所述器件隔离区域，其中执行整个衬底的热处理以使所述第三电介质膜致密化并氧化所述第二电介质膜和所述半导体之间的界面 基质。

    Method of fabricating a semiconductor device including a contact hole between gate electrode structures
    3.
    发明授权
    Method of fabricating a semiconductor device including a contact hole between gate electrode structures 失效
    制造包括栅电极结构之间的接触孔的半导体器件的方法

    公开(公告)号：US6136658A

    公开(公告)日：2000-10-24

    申请号：US891081

    申请日：1997-07-10

    申请人： Naoyuki Shinmura

    发明人： Naoyuki Shinmura

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8247 ,  H01L23/522 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L21/76897

    摘要： A method of fabricating a semiconductor device is provided which requires less distance allowance between gate electrodes and a contact hole, and which can therefore readily promote micro-fine patterning. A gate insulating film, conductive films to be used as material for gate electrodes, and a mask insulating film to be used as an etching mask are sequentially formed in stack on a surface of a semiconductor substrate. The mask insulating film and the conductive films are processed into a gate electrode pattern. An interlayer insulation film is deposited to fill a space between adjacent stacks of the mask insulating film and gate electrodes. The interlayer insulation film is selectively etched relative to the mask insulating film, thereby exposing sides of the mask insulating film. Side wall films are formed on the exposed portions of sides of the mask insulating film. The interlayer insulation film is selectively etched relative to the mask insulating film and side wall films, a contact hole being thereby formed.

    摘要翻译： 提供一种制造半导体器件的方法，其需要在栅电极和接触孔之间较少的距离余量，因此可以容易地促进微细图案化。 栅极绝缘膜，用作栅电极的材料的导电膜和用作蚀刻掩模的掩模绝缘膜在叠层上依次形成在半导体衬底的表面上。 掩模绝缘膜和导电膜被加工成栅电极图案。 沉积层间绝缘膜以填充掩模绝缘膜和栅电极的相邻叠层之间的空间。 相对于掩模绝缘膜选择性地蚀刻层间绝缘膜，从而暴露掩模绝缘膜的侧面。 侧壁膜形成在掩模绝缘膜的侧面的露出部分上。 相对于掩模绝缘膜和侧壁膜选择性地蚀刻层间绝缘膜，从而形成接触孔。

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5314835A

    公开(公告)日：1994-05-24

    申请号：US972914

    申请日：1992-11-06

    申请人： Katsuji Iguchi ,  Seizo Kakimoto ,  Naoyuki Shinmura

    发明人： Katsuji Iguchi ,  Seizo Kakimoto ,  Naoyuki Shinmura

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L27/10844 ,  H01L27/10817 ,  Y10S438/947

    摘要： A semiconductor memory device includes a plurality of memory cells each including a transistor formed on a surface of a semiconductor substrate and having one terminal, and a capacitor formed on the semiconductor substrate and having first and second electrodes, with the first electrode being connected with one terminal of the transistor. The first electrode of the capacitor includes of a principal portion of either a generally rectangular cubic configuration or a generally cup-shaped configuration, a peripheral portion spaced from and surrounding a peripheral side wall of the principal portion and a bottom portion connecting an end of the principal portion with an end of the peripheral portion. On the other hand, the second electrode of the capacitor is includes of respective portions confronting the principal portion, the peripheral portion and the bottom portion of the first electrode.

    摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元包括形成在半导体衬底的表面上并具有一个端子的晶体管，以及形成在半导体衬底上并具有第一和第二电极的电容器，第一电极与一个第一电极连接 晶体管的端子。 电容器的第一电极包括大致矩形立方体形状或大致杯形构造的主要部分，与主要部分的周边侧壁间隔开并围绕主体部分的周边侧壁的周边部分，以及连接端部的底部 主体部分，其周边部分的端部。 另一方面，电容器的第二电极包括面对第一电极的主要部分，周边部分和底部的相应部分。

    Crosspoint structure semiconductor memory device, and manufacturing method thereof
    5.
    发明授权
    Crosspoint structure semiconductor memory device, and manufacturing method thereof 有权
    交叉点结构半导体存储器件及其制造方法

    公开(公告)号：US07687840B2

    公开(公告)日：2010-03-30

    申请号：US11146115

    申请日：2005-06-07

    申请人： Naoyuki Shinmura

    发明人： Naoyuki Shinmura

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/222 ,  H01L21/76838 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

    摘要： A crosspoint structure semiconductor memory device includes a plurality of upper electrode interconnectings extending in the same direction and a plurality of lower electrode interconnectings extending in a direction orthogonal to the extension direction of the upper electrode interconnectings. A storage material member that stores data is formed between the upper electrode interconnectings and the lower electrode interconnectings. At least either the upper electrode interconnectings or the lower electrode interconnectings are formed along sidewall surfaces of projections formed into stripes of an insulation film processed to have the projections.

    摘要翻译： 交叉点结构半导体存储器件包括沿相同方向延伸的多个上电极互连和沿与上电极互连的延伸方向正交的方向延伸的多个下电极互连。 存储数据的存储材料构件形成在上电极互连和下电极互连之间。 至少上部电极互连或下部电极互连中的至少一个沿着形成为加工成具有突起的绝缘膜的条纹的突起的侧壁表面形成。

    Process for forming a trench device isolation region on a semiconductor substrate
    6.
    发明授权
    Process for forming a trench device isolation region on a semiconductor substrate 失效
    在半导体衬底上形成沟槽器件隔离区的工艺

    公开(公告)号：US6060371A

    公开(公告)日：2000-05-09

    申请号：US114498

    申请日：1998-07-13

    申请人： Naoyuki Shinmura

    发明人： Naoyuki Shinmura

    IPC分类号： H01L21/76 ,  H01L21/762

    CPC分类号： H01L21/76232

    摘要： A process for manufacturing a semiconductor device including: forming a mask having a pattern for forming a trench on a semiconductor substrate; forming a film having substantially the same etch rate as the semiconductor substrate on the resulting semiconductor substrate; forming a trench having an inclined sidewall by simultaneously etching the film and a trench formation region on the semiconductor substrate; and embedding an insulating material in the trench thereby to form a device isolation region.

    摘要翻译： 一种制造半导体器件的方法，包括：在半导体衬底上形成具有用于形成沟槽的图案的掩模; 在所得半导体衬底上形成具有与半导体衬底基本相同的蚀刻速率的膜; 通过同时蚀刻所述膜和在所述半导体衬底上的沟槽形成区域形成具有倾斜侧壁的沟槽; 并且将绝缘材料嵌入沟槽中，从而形成器件隔离区域。

    Crosspoint structure semiconductor memory device, and manufacturing method thereof
    7.
    发明申请
    Crosspoint structure semiconductor memory device, and manufacturing method thereof 有权
    交叉点结构半导体存储器件及其制造方法

    公开(公告)号：US20050275003A1

    公开(公告)日：2005-12-15

    申请号：US11146115

    申请日：2005-06-07

    申请人： Naoyuki Shinmura

    发明人： Naoyuki Shinmura

    IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L27/22 ,  H01L27/24 ,  H01L43/08 ,  H01L45/00

    CPC分类号： H01L27/222 ,  H01L21/76838 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

    摘要： A crosspoint structure semiconductor memory device includes a plurality of upper electrode interconnectings extending in the same direction and a plurality of lower electrode interconnectings extending in a direction orthogonal to the extension direction of the upper electrode interconnectings. A storage material member that stores data is formed between the upper electrode interconnectings and the lower electrode interconnectings. At least either the upper electrode interconnectings or the lower electrode interconnectings are formed along sidewall surfaces of projections formed into stripes of an insulation film processed to have the projections.

    摘要翻译： 交叉点结构半导体存储器件包括沿相同方向延伸的多个上电极互连和沿与上电极互连的延伸方向正交的方向延伸的多个下电极互连。 存储数据的存储材料构件形成在上电极互连和下电极互连之间。 至少上部电极互连或下部电极互连中的至少一个沿着形成为加工成具有突起的绝缘膜的条纹的突起的侧壁表面形成。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5334869A

    公开(公告)日：1994-08-02

    申请号：US112480

    申请日：1993-08-27

    申请人： Katsuji Iguchi ,  Seizo Kakimoto ,  Naoyuki Shinmura

    发明人： Katsuji Iguchi ,  Seizo Kakimoto ,  Naoyuki Shinmura

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/68

    CPC分类号： H01L27/10844 ,  H01L27/10817 ,  Y10S438/947

    摘要： A semiconductor memory device includes a plurality of memory cells each including a transistor formed on a surface of a semiconductor substrate and having one terminal, and a capacitor formed on the semiconductor substrate and having first and second electrodes, with the first electrode being connected with one terminal of the transistor. The first electrode of the capacitor includes a principal portion of either a generally rectangular cubic configuration or a generally cup-shaped configuration, a peripheral portion spaced from and surrounding a peripheral side wall of the principal portion and a bottom portion connecting an end of the principal portion with an end of the peripheral portion. On the other hand, the second electrode of the capacitor includes respective portions confronting the principal portion, the peripheral portion and the bottom portion of the first electrode.

    摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元包括形成在半导体衬底的表面上并具有一个端子的晶体管，以及形成在半导体衬底上并具有第一和第二电极的电容器，第一电极与一个第一电极连接 晶体管的端子。 电容器的第一电极包括大致矩形立方体形状或大致杯形构造的主要部分，与主要部分的周边侧壁间隔开并围绕主体部分的周边侧壁的周边部分，以及连接主体端部的底部部分 该部分具有周边部分的端部。 另一方面，电容器的第二电极包括与第一电极的主要部分，周边部分和底部相对的各个部分。