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20 条记录 (耗时 0.012 秒)

    Self-aligned collar and strap formation for semiconductor devices
    1.
    发明授权
    Self-aligned collar and strap formation for semiconductor devices 失效
    用于半导体器件的自对准套环和绑带

    公开(公告)号：US07015145B2

    公开(公告)日：2006-03-21

    申请号：US09756415

    申请日：2001-01-08

    申请人： Venkatachalam C. Jaiprakash ,  Norbert Arnold

    发明人： Venkatachalam C. Jaiprakash ,  Norbert Arnold

    IPC分类号： H01L21/311

    CPC分类号： H01L27/10867 ,  H01L27/10864

    摘要： A method for fabricating a buried strap forms a dielectric collar along sidewalls of a trench. The trench is formed in a substrate. The trench is filled with a conductive material and the conductive material is recessed in the trench to expose a portion of the collar. A masking layer is deposited in the trench over the exposed portion of the collar. A portion of the masking layer is removed over one side of the collar and a portion of the collar is etched on the one side. A buried strap is formed on the conductive material, which connects to the substrate on the one side.

    摘要翻译： 用于制造掩埋带的方法在沟槽的侧壁形成介电轴颈。 沟槽形成在衬底中。 沟槽填充有导电材料，并且导电材料凹陷在沟槽中以暴露套环的一部分。 屏蔽层沉积在套环暴露部分的沟槽中。 屏蔽层的一部分在套环的一侧被移除，并且在一侧蚀刻套环的一部分。 在导电材料上形成掩埋带，该导电材料在一侧连接到基底。

    Anchoring cartridge for anchoring a fastening element in a drilled hole
    3.
    发明授权
    Anchoring cartridge for anchoring a fastening element in a drilled hole 失效
    用于将紧固元件锚定在钻孔中的锚定筒

    公开(公告)号：US5551805A

    公开(公告)日：1996-09-03

    申请号：US192702

    申请日：1994-02-07

    申请人： Norbert Arnold ,  Willi Haug

    发明人： Norbert Arnold ,  Willi Haug

    IPC分类号： C09J5/04 ,  C08J3/24 ,  C08L63/10 ,  C09J5/00 ,  E21D20/00 ,  F16B13/14 ,  E21D20/02

    CPC分类号： C08J3/241 ,  C08L63/10 ,  F16B13/145

    摘要： The anchoring cartridge for anchoring a fastening element in a drilled hole has two chambers. One chamber contains from 1.0 to 10% of a hardener component dissolved in a mixture of styrene and an unaccelerated radical-curing resin and the other chamber contains an accelerator mixed with another mixture of styrene and unaccelerated radical-curing resin. By including unaccererated radical-curing resin in both chambers a homogeneous curing of the components is ensured.

    摘要翻译： 用于将紧固元件锚定在钻孔中的锚定盒具有两个室。 一个室含有溶解在苯乙烯和未加速的自由基固化树脂的混合物中的1.0-10％的固化剂组分，另一个室含有与苯乙烯和未加速的自由基固化树脂的另一混合物混合的促进剂。 通过在两个室中包含无引导剂的自由基固化树脂，确保了组分的均匀固化。

    DRAM with vertical transistor and trench capacitor memory cells and method of fabrication
    4.
    发明授权
    DRAM with vertical transistor and trench capacitor memory cells and method of fabrication 失效
    DRAM具有垂直晶体管和沟槽电容器存储单元及其制造方法

    公开(公告)号：US06849496B2

    公开(公告)日：2005-02-01

    申请号：US10617511

    申请日：2003-07-11

    申请人： Venkatachalam C. Jaiprakash ,  Mihel Seitz ,  Norbert Arnold

    发明人： Venkatachalam C. Jaiprakash ,  Mihel Seitz ,  Norbert Arnold

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10867

    摘要： A semiconductor Dynamic Random Access Memory (DRAM) cell is fabricated using a vertical access transistor and a storage capacitor formed in a vertical trench. A Shallow Trench Isolation (STI) region is used as a masking region to confine the channel region of the access transistor, the first and second output regions of the access transistor, and a strap region connecting the second output region to the storage capacitor, to a narrow portion of the trench. The so confined second output region of the access transistor has reduced leakage to similar second output regions of adjacent memory cells. Adjacent memory cells can then be placed closer to one another without an increase in leakage and cross-talk between adjacent memory cells.

    摘要翻译： 使用垂直存取晶体管和形成在垂直沟槽中的存储电容器制造半导体动态随机存取存储器（DRAM）单元。 浅沟槽隔离（STI）区域用作屏蔽区域，以将存取晶体管的沟道区域，存取晶体管的第一和第二输出区域以及将第二输出区域连接到存储电容器的带区域限制到 沟槽的一小部分。 存取晶体管的如此限制的第二输出区域减少了泄漏到相邻存储器单元的类似的第二输出区域。 相邻的存储器单元然后可以彼此更靠近地放置，而不会增加相邻存储单元之间的泄漏和串扰。

    Memory cell that includes a vertical transistor and a trench capacitor
    5.
    发明授权
    Memory cell that includes a vertical transistor and a trench capacitor 失效

    公开(公告)号：US5937296A

    公开(公告)日：1999-08-10

    申请号：US770962

    申请日：1996-12-20

    申请人： Norbert Arnold

    发明人： Norbert Arnold

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L21/336

    CPC分类号： H01L27/10841

    摘要： A memory cell for a dynamic random access memory includes a pass transistor and a storage capacitor. The transistor is a vertical transistor formed along an upper portion of a sidewall of a polysilicon-filled trench in a monocrystalline silicon body with the source and drain in the body and the source contact, gate and gate contact in the trench, with its gate dielectric being an oxide layer on the sidewall portion of the trench. The capacitor is a vertical capacitor formed along a deeper portion of the trench and has as its storage plate a lower polysilicon layer in the trench and as its reference plate a deep doped well in the body. The source contact and the storage plate are in electrical contact in the trench and the source contact and the gate contact are in the trench electrically isolated from one another.

    Vertical 8F2 cell dram with active area self-aligned to bit line
    8.
    发明授权
    Vertical 8F2 cell dram with active area self-aligned to bit line 失效
    垂直8F2单元格，有源区自对齐到位线

    公开(公告)号：US06884676B2

    公开(公告)日：2005-04-26

    申请号：US10447065

    申请日：2003-05-28

    申请人： Norbert Arnold ,  Venkatachalam C. Jaiprakash

    发明人： Norbert Arnold ,  Venkatachalam C. Jaiprakash

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10864 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

    摘要： A memory cell is formed in a memory cell array comprised of a plurality of memory cells arranged in rows and columns. A deep trench structure is formed within a semiconductor substrate and includes at least one conducting region. A patterned bit line structure is formed atop of, and electrically isolated from, the insulating region of the deep trench structure and atop of, but contacting at least part of, regions of the semiconductor substrate. Exposed portions of the semiconductor substrate are etched to form at least one isolation trench adjoining the deep trench structure using the patterned bit line structure as an etch mask. The isolation trench is filled with a dielectric material. A contact region to the conducting region of the deep trench structure is formed within the dielectric material of the isolation trench and is electrically isolated from the bit line structure. A word line structure that connects to the contact region is formed and is at least partly atop of, but electrically isolated from, the bit line structure.

    摘要翻译： 存储单元形成在由排列成行和列的多个存储单元组成的存储单元阵列中。 深沟槽结构形成在半导体衬底内并且包括至少一个导电区域。 图案化的位线结构形成在深沟槽结构的绝缘区域的顶部并与其电隔离，并且与半导体衬底的至少部分区域接触。 蚀刻半导体衬底的暴露部分，以形成与所述深沟槽结构相邻的至少一个隔离沟槽，使用所述图案化位线结构作为蚀刻掩模。 绝缘沟槽填充有电介质材料。 在深沟槽结构的导电区域的接触区域形成在隔离沟槽的电介质材料内，并且与位线结构电绝缘。 形成连接到接触区域的字线结构，并且至少部分地位于位线结构的顶部，但是与位线结构电隔离。

    Integrated circuit devices including shallow trench isolation
    9.
    发明授权
    Integrated circuit devices including shallow trench isolation 失效
    集成电路器件包括浅沟槽隔离

    公开(公告)号：US5783476A

    公开(公告)日：1998-07-21

    申请号：US883356

    申请日：1997-06-26

    申请人： Norbert Arnold

    发明人： Norbert Arnold

    IPC分类号： H01L21/76 ,  H01L21/318 ,  H01L21/762

    CPC分类号： H01L21/76232

    摘要： A process for forming a silicon oxide-filled shallow trench on the active surface of a silicon chip starts with forming a trench in the silicon chip that has an upper portion with vertical side walls and a lower portion with tapered side walls. Then oxygen is implanted selectively into the walls of the lower portion of the trench and the chip is heated to react the implanted oxygen with the silicon to form silicon oxide. The rest of the trench is then filled with deposited silicon oxide, typically by depositing a layer of silicon oxide over the surface and then planarizing the deposited silicon oxide essentially to the level of the top of the trench. The silicon-filled shallow trench serves to divide the surface portion of the chip into discrete regions, each for housing one or more circuit components of an integrated circuit.

    摘要翻译： 在硅芯片的有源表面上形成氧化硅填充的浅沟槽的工艺首先在硅芯片中形成具有垂直侧壁的上部的沟槽和具有锥形侧壁的下部。 然后选择性地将氧气注入到沟槽下部的壁中，并且加热芯片以使注入的氧气与硅反应以形成氧化硅。 通常通过在表面上沉积氧化硅层，然后将沉积的氧化硅基本平坦化到沟槽顶部的水平面，然后用沉积的氧化硅填充沟槽的其余部分。 填充硅的浅沟槽用于将芯片的表面部分分成离散区域，每个区域用于容纳集成电路的一个或多个电路部件。