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    DRAM with vertical transistor and trench capacitor memory cells and method of fabrication
    1.
    发明授权
    DRAM with vertical transistor and trench capacitor memory cells and method of fabrication 失效
    DRAM具有垂直晶体管和沟槽电容器存储单元及其制造方法

    公开(公告)号：US06849496B2

    公开(公告)日：2005-02-01

    申请号：US10617511

    申请日：2003-07-11

    申请人： Venkatachalam C. Jaiprakash ,  Mihel Seitz ,  Norbert Arnold

    发明人： Venkatachalam C. Jaiprakash ,  Mihel Seitz ,  Norbert Arnold

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10867

    摘要： A semiconductor Dynamic Random Access Memory (DRAM) cell is fabricated using a vertical access transistor and a storage capacitor formed in a vertical trench. A Shallow Trench Isolation (STI) region is used as a masking region to confine the channel region of the access transistor, the first and second output regions of the access transistor, and a strap region connecting the second output region to the storage capacitor, to a narrow portion of the trench. The so confined second output region of the access transistor has reduced leakage to similar second output regions of adjacent memory cells. Adjacent memory cells can then be placed closer to one another without an increase in leakage and cross-talk between adjacent memory cells.

    摘要翻译： 使用垂直存取晶体管和形成在垂直沟槽中的存储电容器制造半导体动态随机存取存储器（DRAM）单元。 浅沟槽隔离（STI）区域用作屏蔽区域，以将存取晶体管的沟道区域，存取晶体管的第一和第二输出区域以及将第二输出区域连接到存储电容器的带区域限制到 沟槽的一小部分。 存取晶体管的如此限制的第二输出区域减少了泄漏到相邻存储器单元的类似的第二输出区域。 相邻的存储器单元然后可以彼此更靠近地放置，而不会增加相邻存储单元之间的泄漏和串扰。

    DRAM with vertical transistor and trench capacitor memory cells and methods of fabrication
    2.
    发明授权
    DRAM with vertical transistor and trench capacitor memory cells and methods of fabrication 失效
    DRAM具有垂直晶体管和沟槽电容器存储单元及其制造方法

    公开(公告)号：US06621112B2

    公开(公告)日：2003-09-16

    申请号：US09731343

    申请日：2000-12-06

    申请人： Venkatachalam C. Jaiprakash ,  Mihel Seitz ,  Norbert Arnold

    发明人： Venkatachalam C. Jaiprakash ,  Mihel Seitz ,  Norbert Arnold

    IPC分类号： H01L27108

    CPC分类号： H01L27/10867

    摘要： A semiconductor Dynamic Random Access Memory (DRAM) cell is fabricated using a vertical access transistor and a storage capacitor formed in a vertical trench. A Shallow Trench Isolation (STI) region is used as a masking region to confine the channel region of the access transistor, the first and second output regions of the access transistor, and a strap region connecting the second output region to the storage capacitor, to a narrow portion of the trench. The so confined second output region of the access transistor has reduced leakage to similar second output regions of adjacent memory cells. Adjacent memory cells can then be placed closer to one another without an increase in leakage and cross-talk between adjacent memory cells.

    摘要翻译： 使用垂直存取晶体管和形成在垂直沟槽中的存储电容器制造半导体动态随机存取存储器（DRAM）单元。 浅沟槽隔离（STI）区域用作屏蔽区域，以将存取晶体管的沟道区域，存取晶体管的第一和第二输出区域以及将第二输出区域连接到存储电容器的带区域限制到 沟槽的一小部分。 存取晶体管的如此限制的第二输出区域减少了泄漏到相邻存储器单元的类似的第二输出区域。 相邻的存储器单元然后可以彼此更靠近地放置，而不会增加相邻存储单元之间的泄漏和串扰。

    DRAM with very shallow trench isolation
    3.
    发明授权
    DRAM with very shallow trench isolation 失效
    DRAM具有非常浅的沟槽隔离

    公开(公告)号：US07034352B2

    公开(公告)日：2006-04-25

    申请号：US10777332

    申请日：2004-02-11

    申请人： Mihel Seitz ,  Venkatachalam C. Jaiprakash

    发明人： Mihel Seitz ,  Venkatachalam C. Jaiprakash

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10867 ,  H01L21/76224 ,  H01L27/10864

    摘要： The methods and structures of the present invention involve providing a vertical dynamic random access memory (DRAM) cell device comprising a buried strap which can be laterally constrained, thereby maintaining freedom from cross talk, even at 6F2 scaling, in the absence of adjacent Shallow Trench Isolation (STI). The methods and structures of the present invention involve the further recognition that the STI can therefore be vertically confined, freed of any need to extend down below the level of the buried strap. The reduction of the buried strap to 1F width and the concomitant reduction in the depth of the STI together permit a significantly reduced aspect ratio, permitting critically improved manufacturability.

    摘要翻译： 本发明的方法和结构包括提供垂直动态随机存取存储器（DRAM）单元装置，其包括可以被横向约束的埋地带，从而即使在6F2缩放下，在没有相邻的浅沟槽的情况下也可以保持免受串扰的自由 隔离（STI）。 本发明的方法和结构涉及进一步的认识，因此STI可以被垂直地限制，而不需要向下延伸到埋藏带的水平以下。 将掩埋带减少到1F宽度并且伴随着STI的深度的降低允许显着减小的纵横比，从而允许严格改进的可制造性。

    Process for protecting array top oxide
    4.
    发明授权
    Process for protecting array top oxide 有权
    保护阵列顶部氧化物的方法

    公开(公告)号：US06509226B1

    公开(公告)日：2003-01-21

    申请号：US09670741

    申请日：2000-09-27

    申请人： Venkatachalam C. Jaiprakash ,  Jack Mandelman ,  Ramachandra Divakaruni ,  Rajeev Malik ,  Mihel Seitz

    发明人： Venkatachalam C. Jaiprakash ,  Jack Mandelman ,  Ramachandra Divakaruni ,  Rajeev Malik ,  Mihel Seitz

    IPC分类号： H01L218242

    CPC分类号： H01L27/10861

    摘要： Processing of a DRAM device containing vertical MOSFET arrays proceeds through planarization of the array gate conductor (GC) polysilicon of the vertical MOSFET to the top surface of the top oxide. A thin polysilicon layer is deposited over the planarized surface and an active area (M) pad nitride and tetraethyl orthosilicate (TEOS) stack is deposited. The M mask is used to open the pad layer to the silicon surface, and shallow trench isolation (STI) etching is used to form isolation trenches. An AA oxidation is performed, the isolation trenches are filled with high density plasma (HDP) oxide and planarized to the top surface of the AA pad nitride. Following isolation trench (IT) planarization, the AA pad nitride is stripped, with the thin silicon layer serving as an etch stop protecting the underlying top oxide. The etch support (ES) nitride liner is deposited, and the ES mask is patterned to open the support areas. The ES nitride, thin polysilicon layer and top oxide are etched from the exposed areas. A sacrificial oxidation is applied along with well implants, support gate oxidation and support gate polysilicon deposition. Using the etch array (EA) mask, the support gate polysilicon is opened in the array. The ES nitride is removed selective to the underlying silicon layer, protecting the top oxide. The gate stack is deposited and patterned and the process continues to completion.

    摘要翻译： 包含垂直MOSFET阵列的DRAM器件的处理通过将垂直MOSFET的阵列栅极导体（GC）多晶硅平坦化到顶部氧化物的顶表面进行。 在平坦化表面上沉积薄多晶硅层，并沉积有源区（M）衬垫氮化物和原硅酸四乙酯（TEOS）堆叠。 M掩模用于将焊盘层打开到硅表面，并且使用浅沟槽隔离（STI）蚀刻来形成隔离沟槽。 执行AA氧化，隔离沟槽填充有高密度等离子体（HDP）氧化物，并且平坦化到AA衬垫氮化物的顶表面。 在隔离沟槽（IT）平坦化之后，剥离AA衬垫氮化物，薄硅层用作保护底层氧化物的蚀刻停止层。 沉积蚀刻载体（ES）氮化物衬垫，并且将ES掩模图案化以打开支撑区域。 从暴露的区域蚀刻ES氮化物，薄多晶硅层和顶部氧化物。 牺牲氧化与井注入一起施加，支持栅极氧化和支撑栅极多晶硅沉积。 使用蚀刻阵列（EA）掩模，在阵列中打开支撑栅极多晶硅。 对于下层硅层选择性地除去ES氮化物，保护顶部氧化物。 沉积栅极堆叠并图案化，并且该工艺继续完成。

    Methods for forming vertical gate transistors providing improved isolation and alignment of vertical gate contacts
    5.
    发明授权
    Methods for forming vertical gate transistors providing improved isolation and alignment of vertical gate contacts 失效
    用于形成垂直栅极晶体管的方法，其提供改进的垂直栅极触点的隔离和对准

    公开(公告)号：US07015092B2

    公开(公告)日：2006-03-21

    申请号：US10740026

    申请日：2003-12-18

    申请人： Venkatachalam C. Jaiprakash ,  Norbert Arnold

    发明人： Venkatachalam C. Jaiprakash ,  Norbert Arnold

    IPC分类号： H01L21/8242

    CPC分类号： H01L29/66666 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/10891

    摘要： Methods and devices that provide improved isolation and alignment of gate conductors or gate contacts of vertical transistors in deep trench memory cells. A method for forming a vertical gate contact of a vertical transistor includes an oxide spacer formation process that prevents defects, such as shorts caused by voids filled with polysilicon, resulting from etching processes that are performed during fabrication of a vertical transistor, and enables formation of well-defined contact plugs for gate contacts, providing improved alignment structures.

    摘要翻译： 提供深沟槽存储单元中垂直晶体管的栅极导体或栅极触点的改进的隔离和对准的方法和装置。 用于形成垂直晶体管的垂直栅极接触的方法包括氧化物间隔物形成工艺，其防止由垂直晶体管制造期间进行的蚀刻工艺导致的缺陷，例如由填充有多晶硅的空隙引起的短路，并且能够形成 用于门触点的良好定义的接触插头，提供改进的对准结构。

    Vertical 8F2 cell dram with active area self-aligned to bit line
    6.
    发明授权
    Vertical 8F2 cell dram with active area self-aligned to bit line 失效
    垂直8F2单元格，有源区自对齐到位线

    公开(公告)号：US06884676B2

    公开(公告)日：2005-04-26

    申请号：US10447065

    申请日：2003-05-28

    申请人： Norbert Arnold ,  Venkatachalam C. Jaiprakash

    发明人： Norbert Arnold ,  Venkatachalam C. Jaiprakash

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10864 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

    摘要： A memory cell is formed in a memory cell array comprised of a plurality of memory cells arranged in rows and columns. A deep trench structure is formed within a semiconductor substrate and includes at least one conducting region. A patterned bit line structure is formed atop of, and electrically isolated from, the insulating region of the deep trench structure and atop of, but contacting at least part of, regions of the semiconductor substrate. Exposed portions of the semiconductor substrate are etched to form at least one isolation trench adjoining the deep trench structure using the patterned bit line structure as an etch mask. The isolation trench is filled with a dielectric material. A contact region to the conducting region of the deep trench structure is formed within the dielectric material of the isolation trench and is electrically isolated from the bit line structure. A word line structure that connects to the contact region is formed and is at least partly atop of, but electrically isolated from, the bit line structure.

    摘要翻译： 存储单元形成在由排列成行和列的多个存储单元组成的存储单元阵列中。 深沟槽结构形成在半导体衬底内并且包括至少一个导电区域。 图案化的位线结构形成在深沟槽结构的绝缘区域的顶部并与其电隔离，并且与半导体衬底的至少部分区域接触。 蚀刻半导体衬底的暴露部分，以形成与所述深沟槽结构相邻的至少一个隔离沟槽，使用所述图案化位线结构作为蚀刻掩模。 绝缘沟槽填充有电介质材料。 在深沟槽结构的导电区域的接触区域形成在隔离沟槽的电介质材料内，并且与位线结构电绝缘。 形成连接到接触区域的字线结构，并且至少部分地位于位线结构的顶部，但是与位线结构电隔离。

    Self-aligned collar and strap formation for semiconductor devices
    7.
    发明授权
    Self-aligned collar and strap formation for semiconductor devices 失效
    用于半导体器件的自对准套环和绑带

    公开(公告)号：US07015145B2

    公开(公告)日：2006-03-21

    申请号：US09756415

    申请日：2001-01-08

    申请人： Venkatachalam C. Jaiprakash ,  Norbert Arnold

    发明人： Venkatachalam C. Jaiprakash ,  Norbert Arnold

    IPC分类号： H01L21/311

    CPC分类号： H01L27/10867 ,  H01L27/10864

    摘要： A method for fabricating a buried strap forms a dielectric collar along sidewalls of a trench. The trench is formed in a substrate. The trench is filled with a conductive material and the conductive material is recessed in the trench to expose a portion of the collar. A masking layer is deposited in the trench over the exposed portion of the collar. A portion of the masking layer is removed over one side of the collar and a portion of the collar is etched on the one side. A buried strap is formed on the conductive material, which connects to the substrate on the one side.

    摘要翻译： 用于制造掩埋带的方法在沟槽的侧壁形成介电轴颈。 沟槽形成在衬底中。 沟槽填充有导电材料，并且导电材料凹陷在沟槽中以暴露套环的一部分。 屏蔽层沉积在套环暴露部分的沟槽中。 屏蔽层的一部分在套环的一侧被移除，并且在一侧蚀刻套环的一部分。 在导电材料上形成掩埋带，该导电材料在一侧连接到基底。

    Nanotube-on-gate FET structures and applications
    9.
    发明授权
    Nanotube-on-gate FET structures and applications 有权
    纳米管栅极FET结构和应用

    公开(公告)号：US07911831B2

    公开(公告)日：2011-03-22

    申请号：US11939316

    申请日：2007-11-13

    申请人： Thomas Rueckes ,  Brent M. Segal ,  Bernhard Vogeli ,  Darren K. Brock ,  Venkatachalam C. Jaiprakash ,  Claude L. Bertin

    发明人： Thomas Rueckes ,  Brent M. Segal ,  Bernhard Vogeli ,  Darren K. Brock ,  Venkatachalam C. Jaiprakash ,  Claude L. Bertin

    IPC分类号： G11C11/50

    CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C23/00 ,  G11C2213/17 ,  H01L27/112 ,  H01L27/11233 ,  H01L27/115 ,  H01L27/11521 ,  H01L51/0048 ,  H01L51/0052

    摘要： Under one aspect, non-volatile transistor device includes a source and drain with a channel in between; a gate structure made of a semiconductive or conductive material disposed over an insulator over the channel; a control gate made of a semiconductive or conductive material; and an electromechanically-deflectable nanotube switching element in fixed contact with one of the gate structure and the control gate structure and is not in fixed contact with the other of the gate structure and the control gate structure. The device has a network of inherent capacitances, including an inherent capacitance of an undeflected nanotube switching element in relation to the gate structure. The network is such that the nanotube switching element is deflectable into contact with the other of the gate structure and the control gate structure in response to signals being applied to the control gate and one of the source region and drain region.

    摘要翻译： 在一个方面，非易失性晶体管器件包括源极和漏极之间的沟道; 由半导体或导电材料制成的栅极结构，设置在通道上方的绝缘体上; 由半导体或导电材料制成的控制门; 以及与栅极结构和控制栅极结构中的一个固定接触并且不与栅极结构和控制栅极结构中的另一个固定接触的机电偏转的纳米管开关元件。 该器件具有固有电容的网络，包括相对于栅极结构的未折射的纳米管开关元件的固有电容。 网络使得纳米管开关元件响应于施加到控制栅极和源极区域和漏极区域之一的信号而偏转成与栅极结构和控制栅极结构中的另一个接触。