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    Memory having parity error correction
    4.
    发明申请
    Memory having parity error correction 失效
    具有奇偶校验纠错的存储器

    公开(公告)号：US20060285412A1

    公开(公告)日：2006-12-21

    申请号：US11259318

    申请日：2005-10-26

    申请人： Klaus Hummler

    发明人： Klaus Hummler

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1006 ,  G06F11/106 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4078 ,  G11C2211/4062

    摘要： A memory includes a sense amplifier segment and a plurality of word lines including a first transfer word line and a second transfer word line complementary to the first transfer word line. The memory includes a plurality of bit lines coupled to the sense amplifier segment and a memory cell located at each cross point of each word line and each bit line. The first transfer word line and the second transfer word line are adapted for simultaneously inverting data bit values stored in memory cells along a failed word line to correct a parity error during self refresh.

    摘要翻译： 存储器包括读出放大器段和包括与第一传送字线互补的第一传送字线和第二传送字线的多个字线。 存储器包括耦合到读出放大器段的多个位线和位于每个字线和每个位线的每个交叉点处的存储器单元。 第一传送字线和第二传输字线适于同时反转沿着故障字线存储在存储器单元中的数据位值，以在自刷新期间校正奇偶校验错误。

    Memory access using multiple activated memory cell rows
    5.
    发明申请
    Memory access using multiple activated memory cell rows 有权
    使用多个激活的内存单元行进行内存访问

    公开(公告)号：US20060133186A1

    公开(公告)日：2006-06-22

    申请号：US11018313

    申请日：2004-12-21

    申请人： Klaus Hummler

    发明人： Klaus Hummler

    IPC分类号： G11C8/00

    CPC分类号： G11C7/1018

    摘要： For one or more disclosed embodiments, a plurality of rows of memory cells in a memory bank are activated, and a column of memory cells in the memory bank is selected to select memory cells common to activated rows and the selected column. At least one of the selected memory cells common to activated rows and the selected column is selectively accessed. The selecting and the selectively accessing are repeated to access memory cells common to activated rows and a plurality of selected columns.

    摘要翻译： 对于一个或多个公开的实施例，存储器组中的多行存储器单元被激活，并且存储器组中的一列存储器单元被选择为选择激活行和所选列的公用存储单元。 选择性地访问激活行和所选列共用的所选存储单元中的至少一个。 重复选择和选择性访问以访问激活行和多个选定列共同的存储单元。