公开(公告)号：US06545623B1

公开(公告)日：2003-04-08

申请号：US09712714

申请日：2000-11-14

申请人： Paul C. Yu

发明人： Paul C. Yu

IPC分类号： H03M112

CPC分类号： H03M1/0673 ,  H03M1/747 ,  H03M1/806 ,  H03M3/464

摘要： A method for use in a system including an analog-to-digital converter subsystem (ADC) and a digital-to-analog converter subsystem (DAC), wherein the ADC samples an input signal at each of a sequence of sample times and provides a sequence of digital outputs representing the magnitude of the sampled input signal. The method is applicable to such systems in which the DAC includes a plurality of elements, such as capacitors or current sources, each connectable in a plurality of different ways in accordance with the digital outputs so as to contribute a portion of an analog output signal corresponding to the digital output, the magnitude of the portion being determined by a way the element is connected. The method is one for shuffling the elements, and includes the following steps. A plurality of coded analog signals are generated based on the input voltage, each such coded analog signal being above or below a predetermined threshold so as to correspond to a way one of the elements is connected. A predetermined sequence of control codes is provided. The coded analog signals are shuffled in accordance with the sequence of control codes. The shuffled coded analog signals are latched as digital values, and the plurality of elements are connected in ways determined in accordance with the shuffled codes.

摘要翻译： 一种在包括模数转换器子系统（ADC）和数模转换器子系统（DAC）的系统中使用的方法，其中ADC对采样时间序列中的每一个采样输入信号，并提供一个 数字输出的序列表示采样的输入信号的幅度。 该方法适用于其中DAC包括诸如电容器或电流源的多个元件的系统，每个元件可根据数字输出以多种不同的方式连接，以便对应于模拟输出信号的一部分 对于数字输出，该部分的大小由元件连接的方式确定。 该方法是用于混洗元素的方法，包括以下步骤。 基于输入电压生成多个编码模拟信号，每个这样的编码模拟信号高于或低于预定阈值，以便对应于元件之一连接的方式。 提供了一个预定的控制代码序列。 编码的模拟信号根据控制代码的顺序进行混洗。 混洗编码的模拟信号被锁存为数字值，并且多个元件以根据混洗码确定的方式连接。

公开(公告)号：US06285309B1

公开(公告)日：2001-09-04

申请号：US09395846

申请日：1999-09-14

申请人： Paul C. Yu

发明人： Paul C. Yu

IPC分类号： H03M138

CPC分类号： H03M1/168

摘要： A multi-stage analog-to-digital converter (“ADC”) for converting an analog input signal to a series of digital values, each having a first plurality of bits, representing the voltage levels of the analog input signal at a corresponding series of sample times. The ADC includes a plurality of analog-to-digital converter stages connected serially in pipeline configuration. One or more of such stages includes an analog-to-digital subconverter, providing a second plurality of bits of the digital value, where the second plurality is smaller than the first plurality, the analog-to-digital subconverter including a plurality of analog-to-digital subconverter substages connected serially in pipeline configuration. Each such subconverter substages provides one or more bits of the second plurality of bits. The nested approach of this invention allows an increased resolution in the first stage of the pipeline which has the benefit of avoidance of capacitor trimming, a more efficient use of the comparators and other circuit components, a relaxation in the comparator offset requirements, and satisfy kT/C noise requirements more easily in submicron low-voltage ADC's.

摘要翻译： 一种用于将模拟输入信号转换成一系列数字值的多级模数转换器（“ADC”），每一数字值具有第一多位，表示在相应系列的模拟输入信号的电压电平 样品时间。 ADC包括以管道配置串联连接的多个模数转换器级。 一个或多个这样的级包括模数转换子转换器，提供数字值的第二多个位，其中第二多个小于第一多个，该模数转换子转换器包括多个模拟 - 数字子转换器， 数字子转换器子系列串行连接在管道配置中。 每个这样的子转换器子级提供第二多个比特的一个或多个比特。 本发明的嵌套方法允许在管道的第一级中增加分辨率，其有利于避免电容器微调，比较器和其他电路组件的更有效的使用，比较器偏移要求的松弛，并且满足kT / C噪声要求更容易在亚微米低压ADC中。

公开(公告)号：US06211805B1

公开(公告)日：2001-04-03

申请号：US09392138

申请日：1999-09-08

申请人： Paul C. Yu

发明人： Paul C. Yu

IPC分类号： H03M166

CPC分类号： H03M1/0668 ,  H03M1/168

摘要： A method for shuffling capacitors from period to sample period in a stage of a multi-stage analog to digital converter (“ADC”). The ADC stage includes a plurality of capacitors usable for storage of charge during a sample phase and for providing during an amplification phase, in conjunction with an amplifier, an output signal having a voltage representing the difference between the digital output voltage level for the stage and the analog input voltage level for the stage. The method includes the following steps. First, the input is provided to the plurality of capacitors during the sample phase to capture and hold the first analog voltage level at a first time in the sample phase. Then, a selected sub-group of the plurality of capacitors is used as feedback capacitors, while a remaining sub-group of the plurality of capacitors is used as digital to analog subconverter (“DASC”) capacitors, in conjunction with the amplifier, the selected sub-group and the remaining sub-group being different sets in adjacent sample periods. The selection of capacitors is performed in accordance with a predetermined capacitor shuffling procedure adapted to convert resulting harmonic distortion associated with capacitor mismatch into noise having a spectral amplitude peak placed outside of a predetermined spectral band.

摘要翻译： 一种用于在多级模数转换器（“ADC”）的级中从时段到采样周期混合电容器的方法。 ADC级包括可用于在采样阶段期间存储电荷的多个电容器，并且用于在放大期间与放大器一起提供具有代表该级的数字输出电压电平与该级的差值的电压的输出信号 该级的模拟输入电压电平。 该方法包括以下步骤。 首先，在采样阶段期间将输入提供给多个电容器，以在采样阶段中的第一时间捕获和保持第一模拟电压电平。 然后，使用多个电容器的选择的子组作为反馈电容器，而多个电容器的剩余子组与放大器一起用作数模转换器（“DASC”）电容器， 选择子组，其余子组是相邻采样周期中的不同集合。 电容器的选择根据预定的电容器改组程序执行，该电容器改组程序适用于将与电容器失配相关联的所得到的谐波失真转换成具有放置在预定光谱带之外的频谱幅度峰值的噪声。

公开(公告)号：US06466153B1

公开(公告)日：2002-10-15

申请号：US09712719

申请日：2000-11-14

申请人： Paul C. Yu

发明人： Paul C. Yu

IPC分类号： H03M138

CPC分类号： H03M1/0673 ,  H03M1/168 ,  H03M1/806

摘要： A method for shuffling capacitors, for application in a stage of a pipelined analog-to-digital converter that samples an input voltage at each of a sequence of sample times and provides a sequence of digital outputs representing the magnitude of the sampled input voltage. The stage includes an amplifier and a plurality of capacitors which may be connected between the input voltage and an AC ground at a first time and which may be connected between the output of the amplifier and an input of the amplifier, or which may be connected between the input of the amplifier and one of a plurality of reference voltage sources at a second time. The method includes the following steps. A plurality of coded input values are provided, each such coded value corresponding to the connection of one of the capacitors between the input of the amplifier and either the at least one voltage sources or the output of the amplifier. A predetermined sequence of control codes is provided. The coded input values are shuffled in accordance with the sequence of control codes. At the second time the plurality of capacitors are connected between the input of the amplifier and the at least one of the reference voltage sources or the output of the amplifier, in accordance with the shuffled coded input values.

摘要翻译： 一种用于混洗电容器的方法，用于在流水线模数转换器的级中应用，其对采样时间序列中的每一个采样输入电压，并提供表示采样输入电压幅度的数字输出序列。 该级包括放大器和多个电容器，其可以在第一时间连接在输入电压和AC地之间，并且可以连接在放大器的输出端和放大器的输入端之间，或者可以连接在 放大器的输入和多个参考电压源中的一个在第二时间。 该方法包括以下步骤。 提供多个编码输入值，每个这样的编码值对应于放大器的输入端与该至少一个电压源或放大器的输出端之间的一个电容器的连接。 提供了一个预定的控制代码序列。 编码输入值根据控制代码的顺序进行混洗。 在第二次，根据混洗后的编码输入值，多个电容器连接在放大器的输入端与参考电压源的至少一个或放大器的输出端之间。

公开(公告)号：US06456223B1

公开(公告)日：2002-09-24

申请号：US09715228

申请日：2000-11-17

申请人： Paul C. Yu ,  Shereef Shehata ,  Ranjit Gharpurey

发明人： Paul C. Yu ,  Shereef Shehata ,  Ranjit Gharpurey

IPC分类号： H03M138

CPC分类号： H03M1/08 ,  H03M1/0673 ,  H03M1/168

摘要： In a pipelined analog-to-digital converter (ADC) having an analog input signal and a digital output signal, and having a plurality of pipelined stages, each such stage having an analog input, an analog output comprising a residue voltage, and a digital output, the stage including a digital-to-analog converter substage having a plurality of capacitors and which are used in a sample-and-hold function and shuffled according to a predetermined procedure, a method for reducing noise generated from the shuffling when the capacitors are mismatched. The method includes the following steps. First, an estimation model is provided of the noise generated from the shuffling. The estimation model includes factors corresponding to mismatches of the capacitors. Mismatches among capacitors in the stage are estimated, based on the monitoring of an output parameter of the stage. A cancellation factor is generated by applying the mismatch estimations to the estimation model. Finally, the cancellation factor is subtracted from an ADC output to substantially reduce and/or effectively cancel the mismatch noise.

摘要翻译： 在具有模拟输入信号和数字输出信号并且具有多个流水线级的流水线模数转换器（ADC）中，每个这样的级具有模拟输入，包括残余电压的模拟输出和数字 输出，所述级包括具有多个电容器的数模转换器子级，其根据预定的过程用于采样保持功能并进行混洗;一种用于在电容器中减少由混洗产生的噪声的方法 不匹配。 该方法包括以下步骤。 首先，提供从混洗产生的噪声的估计模型。 估计模型包括与电容器不匹配相对应的因素。 基于对该阶段的输出参数的监视来估计阶段中的电容器之间的不匹配。 通过将不匹配估计应用于估计模型来生成消除因子。 最后，从ADC输出中减去消除因子，以显着减少和/或有效地消除失配噪声。

公开(公告)号：US06420991B1

公开(公告)日：2002-07-16

申请号：US09391968

申请日：1999-09-08

申请人： Paul C. Yu

发明人： Paul C. Yu

IPC分类号： H03M138

CPC分类号： H03M1/0673 ,  H03M1/168 ,  H03M1/806

摘要： A method for practice in a pipelined analog to digital converter. The method converts an analog signal to a sequence of digital words, while converting capacitor mismatch in the stages of the ADC into white noise. In the method, for each of one or more of the pipelined stages, first, the plurality of capacitors therein is coupled at a sample time between the stage input port and ground. Second, during an amplifying period following the sample time, one or more of the plurality of capacitors are coupled between a reference voltage and the input port of the amplifier, while the remainder of the plurality of capacitors are coupled between the input port of the amplifier and the output port of the amplifier, such that different ones of the plurality of capacitors are selected, according to a predetermined procedure uncorrelated with the analog signal, for coupling between the stage input port and ground.

摘要翻译： 一种在流水线模数转换器中实践的方法。 该方法将模拟信号转换为数字字序列，同时将ADC级的电容失配转换为白噪声。 在该方法中，对于一个或多个流水线级中的每一个，首先，其中的多个电容器在级输入端口和地之间的采样时间耦合。 第二，在采样时间之后的放大期间，多个电容器中的一个或多个耦合在参考电压和放大器的输入端口之间，而多个电容器的其余部分耦合在放大器的输入端口 和放大器的输出端口，使得根据与模拟信号不相关的预定过程来选择多个电容器中的不同电容器，用于在级输入端口和地之间耦合。

公开(公告)号：US6140948A

公开(公告)日：2000-10-31

申请号：US212014

申请日：1998-12-15

申请人： Paul C. Yu

发明人： Paul C. Yu

IPC分类号： H03M1/10 ,  H03M1/46 ,  H03M1/80 ,  H03M1/06

CPC分类号： H03M1/1019 ,  H03M1/466 ,  H03M1/804

摘要： An analog-to-digital converter system 10 is provided that comprises two separate banks of capacitors that are configured with a single operational amplifier 30 for each stage 29 within the system 10. The banks of capacitors are used in an interleaved fashion to simultaneously digitize analog input voltages and sample a reference voltage V.sub.REF to enable the digitization of a gain error associated with the operation of amplifier 30. This gain error can be combined with the raw digital output of the converter using an arithmetic logic unit 18 to result in a calibrated output for the system 10.

摘要翻译： 提供了模数转换器系统10，其包括两个单独的电容器组，其被配置有用于系统10内的每个级29的单个运算放大器30.电容器组以交错方式使用以同时数字化模拟 输入电压并对参考电压VREF进行采样，以使与放大器30的操作相关联的增益误差的数字化。该增益误差可以与转换器的原始数字输出结合使用运算逻辑单元18以产生校准输出 对于系统10。

公开(公告)号：US06198423B1

公开(公告)日：2001-03-06

申请号：US09211906

申请日：1998-12-15

申请人： Paul C. Yu

发明人： Paul C. Yu

IPC分类号： H03M112

CPC分类号： H03M1/1038 ,  H03M1/167 ,  H03M1/442

摘要： An analog-to-digital converter system 10 is provided that comprises an analog-to-digital converter pipeline 12 coupled to a memory system 14 and a calibration system 16. An arithmetic logic unit 18 receives a raw output from the analog-to-digital converter system 12 and calibration quantities from the calibration system 16 to generate a calibrated output. The calibration system 16 is able to iteratively generate multiple order calibration values that can be used to eliminate capacitor mismatch errors. The techniques described are equally applicable to analog-to-digital converter architectures which resolve multiple bits per stage of the analog-to-digital converter system.

摘要翻译： 提供了一种模数转换器系统10，其包括耦合到存储器系统14和校准系统16的模拟 - 数字转换器流水线12.算术逻辑单元18接收来自模数转换器 转换器系统12和来自校准系统16的校准量以产生校准输出。 校准系统16能够迭代地产生可用于消除电容器失配误差的多个阶校准值。 所描述的技术同样适用于解码模数转换器系统的每个级的多个比特的模数转换器架构。

公开(公告)号：US06184809B2

公开(公告)日：2001-02-06

申请号：US09241879

申请日：1999-02-01

申请人： Paul C. Yu

发明人： Paul C. Yu

IPC分类号： H03M110

CPC分类号： H03M1/1004 ,  H03M1/0658 ,  H03M1/168

摘要： A user transparent self-calibration technique for an analog to digital converter is described. The technique can correct for capacitor mismatch error with minimal additional power consumption. This is done by generating a calibration signal, one for each capacitor whose calibration is desired. The signal is interleaved with the input signal, and digitized by alternating with the input signal digitization using capacitor arrays.

摘要翻译： 描述了用于模数转换器的用户透明自校准技术。 该技术可以以最小的附加功耗来校正电容器失配误差。 这通过产生校准信号来完成，对于需要校准的每个电容器来说，这是一个校准信号。 该信号与输入信号进行交织，并通过与使用电容器阵列的输入信号数字化交替进行数字化。

公开(公告)号：US06348888B1

公开(公告)日：2002-02-19

申请号：US09273837

申请日：1999-03-22

申请人： Paul C. Yu

发明人： Paul C. Yu

IPC分类号： H03M138

CPC分类号： H03M1/0634 ,  H03M1/164 ,  H03M1/44

摘要： A pipelined analog to digital converter for converting an analog signal to a sequence of digital words, each such word representing a value of the analog signal at a time in a succession of times. The converter includes a sequence of analog to digital converter stages, each such stage generating at least one bit for each such word. A first such stage in the sequence receives the analog signal, and each such stage subsequent to the first stage receives a residue signal from a previous stage in the sequence. Each such stage includes an analog to digital unit that senses a sample of the analog signal and provides one or more bits representing a value of the sample. In at least one of the stages the analog to digital unit comprises a &Sgr;-&Dgr; converter.

摘要翻译： 一种用于将模拟信号转换为数字字序列的流水线模数转换器，每个这样的字表示一次中的模拟信号的值。 该转换器包括一系列模数转换器级，每个这样的级产生每个这样的字的至少一位。 序列中的第一个这样的阶段接收模拟信号，并且在第一级之后的每个这样的级从序列中的前一级接收残留信号。 每个这样的级包括模拟数字单元，其感测模拟信号的采样并提供表示样本值的一个或多个位。 在至少一个级中，模数转换单元包括一个SIGMA-DELTA转换器。