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    SIGNAL PROCESSING DEVICE
    1.
    发明申请
    SIGNAL PROCESSING DEVICE 审中-公开
    信号处理装置

    公开(公告)号：US20150241524A1

    公开(公告)日：2015-08-27

    申请号：US14708802

    申请日：2015-05-11

    Applicant: ASAHI KASEI KABUSHIKI KAISHA

    Inventor： Hiroyuki Sasaki ,  Masaya Yamashita

    IPC: G01R33/00

    CPC classification number: H03M1/0634 ,  G01D3/028 ,  G01R33/0029 ,  H03M1/002 ,  H03M1/0863 ,  H03M1/1245

    Abstract: There is provided a signal processing device comprising a combination unit (3) configured to combine plural element signals based on plural physical quantity signals including signal components in accordance with desired physical quantities, respectively, by the number of times equal to or greater than a number of the plural physical quantity signals, and to output combined signals different from each other; a measuring unit (4) configured to sequentially receive the combined signals output from the combination unit (3); and a computing unit (5) configured to compute signal components based on the desired physical quantities from signals that are generated based on the combined signals sequentially output from the measuring unit.

    Abstract translation: 提供了一种信号处理装置，包括组合单元（3），其被配置为基于包括根据期望物理量的信号分量的多个物理量信号组合多个元素信号等于或大于数量的次数 并输出不同的组合信号; 测量单元（4），被配置为顺序地接收从所述组合单元（3）输出的组合信号; 以及计算单元（5），被配置为基于从基于从所述测量单元顺序输出的组合信号生成的信号，基于所述期望物理量来计算信号分量。

    Semiconductor device
    2.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US07498967B2

    公开(公告)日：2009-03-03

    申请号：US11808623

    申请日：2007-06-12

    Applicant: Masaya Hirose ,  Kinya Daio ,  Tetsuya Oosaka ,  Tomoko Nobekawa

    Inventor： Masaya Hirose ,  Kinya Daio ,  Tetsuya Oosaka ,  Tomoko Nobekawa

    IPC: H03M1/12

    CPC classification number: H03M1/108 ,  H03M1/0634 ,  H03M1/109

    Abstract: The semiconductor device includes: an A/D conversion circuit for A/D-converting an analog input signal and outputting a resultant conversion result; and a computation circuit for performing, in synchronization with the A/D conversion circuit, computation for an updated conversion result without storing the updated conversion result every time the conversion result from the A/D conversion circuit is updated, to determine one computation result from a plurality of conversion results from the A/D conversion circuit and output the computation result.

    Abstract translation: 半导体器件包括：A / D转换电路，用于对模拟输入信号进行A / D转换并输出所得到的转换结果; 以及计算电路，用于与A / D转换电路同步地执行更新的转换结果的计算，而不是每当A / D转换电路的转换结果被更新时存储更新的转换结果，从而确定一个计算结果 来自A / D转换电路的多个转换结果并输出计算结果。

    Digital-to-analog converter of the pulse width modulation type
    3.
    发明授权
    Digital-to-analog converter of the pulse width modulation type 失效
    数模转换器的脉宽调制型

    公开(公告)号：US4233591A

    公开(公告)日：1980-11-11

    申请号：US916565

    申请日：1978-06-19

    Applicant: Toshinori Murata ,  Shigeo Matsuura ,  Hiroshi Miyamoto ,  Eisaku Akutsu

    Inventor： Toshinori Murata ,  Shigeo Matsuura ,  Hiroshi Miyamoto ,  Eisaku Akutsu

    IPC: H03M1/82 ,  H03M1/00 ,  H03M1/68 ,  H03K13/02

    CPC classification number: H03M1/822 ,  H03M1/0634

    Abstract: A digital-to-analog converter of a pulse width modulation type in which a single counting cycle of a clock pulse counter is divided into 2.sup.m elementary periods where m represents a selected number of less significant bits of a digital input data to be converted into analog quantity and elementary pulses in number determined in dependence on the logic values of the more significant bits are distributed among the elementary periods, while supplementary elementary pulses are produced in the elementary periods selected in dependence on the logic values of the less significant bits of the digital input data. These elementary pulses are integrated for every elementary period and the integrated output value is converted into a corresponding DC analog output signal.

    Abstract translation: 一种脉冲宽度调制型的数/模转换器，其中时钟脉冲计数器的单个计数周期被划分为2m个基本周期，其中m表示要转换为模拟的数字输入数据的选定数量的较低有效位 根据更高有效位的逻辑值确定的数量和基本脉冲数量分布在基本周期之间，而辅助基本脉冲则是根据数字的较低有效位的逻辑值选择的基本周期产生的 输入数据。 对于每个基本周期，这些基本脉冲被积分，并且积分输出值被转换成相应的直流模拟输出信号。

    Cyclic ADC with voting and adaptive averaging
    4.
    发明授权
    Cyclic ADC with voting and adaptive averaging 有权

    公开(公告)号：US12040807B2

    公开(公告)日：2024-07-16

    申请号：US17576681

    申请日：2022-01-14

    Applicant: Senbiosys

    Inventor： Assim Boukhayma ,  Massimiliano Bracco ,  Antonino Caizzone

    IPC: H03M1/34 ,  H03M1/00 ,  H03M1/06

    CPC classification number: H03M1/002 ,  H03M1/0634

    Abstract: A cyclic analog to digital converter for digitizing an output from a photoplethysmography sensor has a buffer amplifier for setting a voltage of the feedback capacitance. Additionally, digital averaging circuit is preferably provided for averaging the digital output from the cyclic analog to digital converter for the several conversions. Finally, voting logic is additionally provided for declaring the digital bits based on successive comparisons by the one or more comparators.

    A/D converter circuit and semiconductor integrated circuit
    5.
    发明授权
    A/D converter circuit and semiconductor integrated circuit 有权

    公开(公告)号：US10020814B2

    公开(公告)日：2018-07-10

    申请号：US15594753

    申请日：2017-05-15

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Keisuke Kimura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto

    IPC: H03M1/06 ,  H03M1/10 ,  H03M1/12 ,  H03M1/00

    CPC classification number: H03M1/0634 ,  H03M1/002 ,  H03M1/0617 ,  H03M1/1009 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1225

    Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.

    A/D converter circuit and semiconductor integrated circuit
    7.
    发明授权
    A/D converter circuit and semiconductor integrated circuit 有权

    公开(公告)号：US09685968B2

    公开(公告)日：2017-06-20

    申请号：US15142273

    申请日：2016-04-29

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Keisuke Kimura ,  Yuichi Okuda ,  Hideo Nakane ,  Takaya Yamamoto

    IPC: H03M1/06 ,  H03M1/10 ,  H03M1/00 ,  H03M1/12

    CPC classification number: H03M1/0634 ,  H03M1/002 ,  H03M1/0617 ,  H03M1/1009 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1225

    Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.

    Method and system for implementing correlated multi-sampling with improved analog-to-digital converter linearity
    9.
    发明授权
    Method and system for implementing correlated multi-sampling with improved analog-to-digital converter linearity 有权
    用于实现具有改进的模数转换器线性度的相关多重采样的方法和系统

    公开(公告)号：US09491390B2

    公开(公告)日：2016-11-08

    申请号：US14555062

    申请日：2014-11-26

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Robert Johansson

    IPC: H04N5/378 ,  H04N5/357 ,  H03M1/06

    CPC classification number: H04N5/378 ,  H03M1/0634 ,  H04N5/3575

    Abstract: A method of implementing Correlated Multi-Sampling (CMS) in an image sensor with improved analog-to-digital converter (ADC) linearity starts with an ADC circuitry included in a readout circuitry that generates a plurality of uncorrelated random numbers used as a plurality of ADC pedestals for sampling image data. A Successive Approximation Register (SAR) included in the ADC circuitry stores a different one of the ADC pedestals before each sampling of the image data. The ADC circuitry samples an image data from a row a plurality of times against plurality of ADC pedestals to obtain a plurality of sampled input data. The ADC circuitry converts each of the plurality of sampled input data from analog to digital, which includes performing a binary search using the SAR. Other embodiments are also described.

    Abstract translation: 在具有改进的模数转换器（ADC）线性的图像传感器中实现相关多采样（CMS）的方法从包括在读出电路中的ADC电路开始，该读出电路产生多个不相关的随机数作为多个 用于采样图像数据的ADC基座。 ADC电路中包含的连续近似寄存器（SAR）在每次采样图像数据之前存储不同的ADC基座。 ADC电路对多个ADC基座多次对来自行的图像数据进行采样，以获得多个采样的输入数据。 ADC电路将多个采样输入数据中的每一个从模拟转换为数字，其中包括使用SAR执行二进制搜索。 还描述了其它实施例。

    Digitizer auto aperture with trigger spacing
    10.
    发明授权
    Digitizer auto aperture with trigger spacing 有权
    数位转换器带有触发间距的自动光圈

    公开(公告)号：US09197236B1

    公开(公告)日：2015-11-24

    申请号：US14568904

    申请日：2014-12-12

    Applicant: Keithley Instruments, Inc.

    Inventor： Wayne C. Goeke ,  Brian P. Frackelton ,  Benjamin J. Yurick

    IPC: G01R13/02 ,  H03M1/12 ,  H03M1/06

    CPC classification number: H03M1/20 ,  G01R13/0254 ,  G01R13/0272 ,  G01R19/2509 ,  H03M1/005 ,  H03M1/0634 ,  H03M1/0658 ,  H03M1/1245 ,  H03M1/1265

    Abstract: A method for producing sampled data, which as the requested sampling period is increased, each sample is the average of an increasing number of ADC samples such that a maximum number of ADC samples are evenly space across the sample period. The method can include choosing one of multiple ADC with varying speed versus resolution capabilities to further increase the quality of the sampled data as the sampling period increases.

    Abstract translation: 一种用于产生采样数据的方法，其随着所请求的采样周期的增加，每个样本是越来越多的ADC采样的平均值，使得ADC采样的最大数量在采样周期内是均匀的空间。 该方法可以包括选择具有不同速度与分辨率能力的多个ADC中的一个，以在采样周期增加时进一步提高采样数据的质量。

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