Monolithically integrated mos output-stage component having an
excess-temperature protection device
    2.
    发明授权
    Monolithically integrated mos output-stage component having an excess-temperature protection device 失效
    具有过温保护装置的整体式MOS输出级元件

    公开(公告)号:US5555152A

    公开(公告)日:1996-09-10

    申请号:US136627

    申请日:1993-10-14

    摘要: A monolithically integrated MOS output-stage component, particularly a DMOS output stage, includes an output-stage element having a GATE connection, a SOURCE connection, and a DRAIN connection, and also includes an excess-temperature protection device. An integrated GATE-protection resistor is provided. The excess-temperature protection device is also integrated in the output-stage component and includes a series connection of a Zener-diode with a temperature-dependent resistor having a positive temperature coefficient. The resistor is coupled with the SOURCE connection while the Zener-diode is coupled with an outer GATE connection. The series connection is provided with a supply voltage. Furthermore, the excess-temperature protection device contains a semiconductor arrangement controlled by a control voltage at the tap node of the series connection. The semiconductor arrangement reduces the GATE voltage upon the occurrence of excess temperatures. In this way, an evaluation signal having a high total slope with respect to temperature is obtained with only slight requirements for the temperature-dependent resistor. Tank leakage currents are compensated for. The output-stage component is completely integratable in a simple manner and, thus, can be manufactured at favorable cost.

    摘要翻译: 单片集成MOS输出级组件,特别是DMOS输出级,包括具有GATE连接,SOURCE连接和DRAIN连接的输出级元件,并且还包括过温保护器件。 提供集成的GATE保护电阻。 过温保护器件也集成在输出级元件中,包括齐纳二极管与具有正温度系数的温度依赖电阻器的串联连接。 电阻器与SOURCE连接耦合,而齐纳二极管与外部GATE连接耦合。 串联连接提供电源电压。 此外,过温保护装置包含由串联连接的抽头节点处的控制电压控制的半导体装置。 半导体装置在发生过温时会降低GATE电压。 以这种方式,仅对温度依赖性电阻器的要求略微得到相对于温度具有高总斜率的评估信号。 油箱泄漏电流得到补偿。 输出级部件以简单的方式可完全集成,因此可以以有利的成本制造。

    Monolithically integrated circuit
    3.
    发明授权
    Monolithically integrated circuit 失效
    单片集成电路

    公开(公告)号:US5432371A

    公开(公告)日:1995-07-11

    申请号:US167839

    申请日:1993-12-20

    摘要: A monolithically integrated circuit arrangement is arranged in a disc-shaped monocrystalline semiconductor body (100) of a first conductivity type, which semiconductor body consists of silicon and has a first and second main surface. The monolithically integrated circuit arrangement contains a vertical MOSFET power transistor (T1) which consists of a plurality of partial transistors connected in parallel and surrounded by a guard ring (4) of a second conductivity type opposite that of the semiconductor body (100). Proceeding from the first main surface (13), at least one zone (7, 8) of the conductivity type of the semiconductor body (100) but of increased impurity concentration is diffused into the guard ring (4) so as to form at least one active and/or passive peripheral circuit element (T2) which has a protective and/or regulating and/or control function.

    摘要翻译: PCT No.PCT / DE92 / 00479 Sec。 371日期:1993年12月20日 102(e)日期1993年12月20日PCT提交1992年6月10日PCT公布。 公开号WO93 / 00709 日期:1993年1月7日。单片集成电路布置在第一导电类型的盘状单晶体半导体本体(100)中,该半导体主体由硅组成并具有第一和第二主表面。 单片集成电路装置包括垂直MOSFET功率晶体管(T1),其由并联连接并由与半导体本体(100)相反的第二导电类型的保护环(4)包围的多个部分晶体管组成。 从第一主表面(13)开始,半导体主体(100)的导电类型的至少一个区域(7,8)扩散到保护环(4)中,以至少形成 具有保护和/或调节和/或控制功能的一个有源和/或无源外围电路元件(T2)。

    Arrangement for testing a gate oxide
    4.
    发明授权
    Arrangement for testing a gate oxide 失效
    用于测试栅极氧化物的布置

    公开(公告)号:US5770947A

    公开(公告)日:1998-06-23

    申请号:US619755

    申请日:1996-03-27

    申请人: Peter Brauchle

    发明人: Peter Brauchle

    IPC分类号: G01R31/27 G01R31/28 G01R31/26

    CPC分类号: G01R31/275 G01R31/2884

    摘要: A circuit arrangement has an integrated monocrystaline semiconductor power component having a gate, a first measuring pad, a second measuring pad, and a resistor arranged so that the gate of the power component is connected with the first measuring pad while the first measuring pad is connected with the resistor, the first measuring pad being charged with a gate test voltage which is greater than a gate voltage required for operation of the power component, the power component being integrated with an integrated circuit on a chip, the integrated circuit being connected with the second measuring pad, while the second measuring pad is connected with the resistor, the second measuring pad being charged with an external voltage which is compatible with the integrated circuit.

    摘要翻译: PCT No.PCT / DE94 / 01199 Sec。 371日期:1996年3月27日 102(e)1996年3月27日PCT 1994年10月6日PCT PCT。 公开号WO95 / 10785 日期1995年04月20日电路布置具有集成的单晶半导体功率元件,具有栅极,第一测量焊盘,第二测量焊盘和电阻器,其被布置成使得功率部件的栅极与第一测量垫连接, 第一测量垫与电阻器连接,第一测量垫被充以栅极测试电压,该栅极测试电压大于功率部件操作所需的栅极电压,功率部件与芯片上的集成电路集成,集成 电路与第二测量垫连接,而第二测量垫与电阻器连接,第二测量垫被充满与集成电路兼容的外部电压。