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14 条记录 (耗时 0.026 秒)

    Method and apparatus with varying gate oxide thickness
    4.
    发明申请
    Method and apparatus with varying gate oxide thickness 有权
    具有不同栅极氧化物厚度的方法和装置

    公开(公告)号：US20060237784A1

    公开(公告)日：2006-10-26

    申请号：US11114455

    申请日：2005-04-25

    申请人： Irfan Rahim ,  Yow-Juang Liu ,  Jeffrey Watt

    发明人： Irfan Rahim ,  Yow-Juang Liu ,  Jeffrey Watt

    IPC分类号： H01L29/76

    CPC分类号： H01L27/0203 ,  H01L21/823857 ,  H01L27/0922 ,  H01L27/11807 ,  H01L27/11898 ,  Y10S257/903

    摘要： An integrated circuit having an enhanced on-off swing for pass gate transistors is provided. The integrated circuit includes a core region that includes core transistors and pass gate transistors. The core transistors have a gate oxide associated with a first thickness, the pass transistors having a gate oxide associated with a thickness that is less than the first thickness. In one embodiment, the material used for the gate oxide of the pass gate transistors has a dielectric constant that is greater than four, while the material used for the gate oxide of the core transistors has a dielectric constant that is less than or equal to four. A method for manufacturing an integrated circuit is also provided.

    摘要翻译： 提供了一种具有用于通过栅极晶体管的增强的通断摆幅的集成电路。 集成电路包括具有核心晶体管和栅极晶体管的核心区域。 核心晶体管具有与第一厚度相关的栅极氧化物，所述通过晶体管具有与小于第一厚度的厚度相关联的栅极氧化物。 在一个实施例中，用于栅极晶体管的栅极氧化物的材料具有大于4的介电常数，而用于核心晶体管的栅极氧化物的材料具有小于或等于4的介电常数 。 还提供了一种用于制造集成电路的方法。

    Memory element circuitry with stressed transistors
    6.
    发明授权
    Memory element circuitry with stressed transistors 有权
    具有应力晶体管的存储元件电路

    公开(公告)号：US08218353B1

    公开(公告)日：2012-07-10

    申请号：US12561236

    申请日：2009-09-16

    申请人： Jun Liu ,  Shankar Sinha ,  Qi Xiang ,  Yow-Juang Liu

    发明人： Jun Liu ,  Shankar Sinha ,  Qi Xiang ,  Yow-Juang Liu

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412

    摘要： Integrated circuits with memory elements are provided. The memory elements may be arranged in a memory block. The memory block may include cross-coupled inverters that store data. The stored data may be used to program pass transistors. Transistors in the memory block may be stressed. Depending on the type of stress-inducing layer used, a tensile stress or a compressive stress may be built in into the transistors. Stressed transistors may help improve the routing speed of the memory block. Stressed transistors may be implemented using dual gate-oxide process.

    摘要翻译： 提供具有存储元件的集成电路。 存储器元件可以被布置在存储器块中。 存储器块可以包括存储数据的交叉耦合的反相器。 存储的数据可用于编程传输晶体管。 存储器块中的晶体管可能受到压力。 根据所使用的应力诱导层的类型，可以将内部的拉伸应力或压应力内置到晶体管中。 受压的晶体管可能有助于提高存储器块的布线速度。 可以使用双栅极氧化工艺来实施受压晶体管。

    Electrically-programmable transistor antifuses
    7.
    发明授权
    Electrically-programmable transistor antifuses 有权
    电可编程晶体管反熔丝

    公开(公告)号：US07157782B1

    公开(公告)日：2007-01-02

    申请号：US10780427

    申请日：2004-02-17

    申请人： Chih-Ching Shih ,  Cheng H. Huang ,  Hugh Sung-Ki O ,  Yow-Juang Liu

    发明人： Chih-Ching Shih ,  Cheng H. Huang ,  Hugh Sung-Ki O ,  Yow-Juang Liu

    IPC分类号： H01L29/00 ,  H01L29/04 ,  H01L29/10 ,  H01L31/036 ,  H01L23/58

    CPC分类号： H01L29/78 ,  H01L27/0203 ,  H01L27/112 ,  H01L27/11206

    摘要： Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) transistor serves as an electrically-programmable antifuse. The antifuse transistor has source, drain, gate, and substrate terminals. The gate has an associated gate oxide. In its unprogrammed state, the gate oxide is intact and the antifuse has a relatively high resistance. During programming, the gate oxide breaks down, so in its programmed state the antifuse transistor has a relatively low resistance. The antifuse transistor can be programmed by injecting hot carriers into the substrate of the device in the vicinity of the drain. Because there are more hot carriers at the drain than at the substrate, the gate oxide is stressed asymmetrically, which enhances programming efficiency. Feedback can be used to assist in turning the antifuse transistor on to inject the hot carriers.

    摘要翻译： 提供集成电路反熔丝电路。 金属氧化物半导体（MOS）晶体管用作电可编程反熔丝。 反熔丝晶体管具有源极，漏极，栅极和衬底端子。 栅极具有相关的栅极氧化物。 在其未编程状态下，栅极氧化物是完整的，并且反熔丝具有相对较高的电阻。 在编程期间，栅极氧化物分解，因此在其编程状态下，反熔丝晶体管具有相对低的电阻。 可以通过将热载流子注入到漏极附近的器件的衬底中来编程反熔丝晶体管。 由于漏极处的热载流子比衬底上的热载流子多，所以栅极氧化物不对称地受到应力，从而提高了编程效率。 可以使用反馈来帮助反熔丝晶体管打开以注入热载体。

    APPARATUS AND METHODS FOR MULTI-GATE SILICON-ON-INSULATOR TRANSISTORS
    8.
    发明申请
    APPARATUS AND METHODS FOR MULTI-GATE SILICON-ON-INSULATOR TRANSISTORS 有权
    多栅极绝缘体晶体管的装置和方法

    公开(公告)号：US20060279333A1

    公开(公告)日：2006-12-14

    申请号：US11466565

    申请日：2006-08-23

    申请人： Minchang Liang ,  Yow-Juang Liu

    发明人： Minchang Liang ,  Yow-Juang Liu

    IPC分类号： H03K19/0175

    CPC分类号： G06F17/5054 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78648 ,  H03K17/6871 ,  H03K17/693 ,  H03K2217/0018

    摘要： An integrated circuit (IC) includes mechanisms for adjusting or setting the gate bias of one gate of one or more multi-gate transistors. The IC includes a gate bias generator. The gate bias generator is configured to set a gate bias of one gate of the one or more multi-gate transistors within the IC. More specifically, the gate bias generator sets the gate bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).

    摘要翻译： 集成电路（IC）包括用于调整或设置一个或多个多栅极晶体管的一个栅极的栅极偏置的机构。 IC包括栅极偏置发生器。 栅极偏置发生器被配置为设置IC内的一个或多个多栅极晶体管的一个栅极的栅极偏置。 更具体地，栅极偏置发生器设置晶体管的栅极偏置，以便折衷晶体管的性能和功耗。

    Compact SCR device and method for integrated circuits
    9.
    发明授权
    Compact SCR device and method for integrated circuits 有权
    集成电路的紧凑型SCR器件和方法

    公开(公告)号：US07342282B2

    公开(公告)日：2008-03-11

    申请号：US10938102

    申请日：2004-09-10

    申请人： Hugh Sungki O ,  Chih-Ching Shih ,  Cheng-Hsiung Huang ,  Yow-Juang Liu

    发明人： Hugh Sungki O ,  Chih-Ching Shih ,  Cheng-Hsiung Huang ,  Yow-Juang Liu

    IPC分类号： H01L29/74

    CPC分类号： H01L27/0262 ,  H01L29/74

    摘要： A semiconductor device and method for electrostatic discharge protection. The semiconductor device includes a first semiconductor controlled rectifier and a second semiconductor controlled rectifier. The first semiconductor controlled rectifier includes a first semiconductor region and a second semiconductor region, and the second semiconductor controlled rectifier includes the first semiconductor region and the second semiconductor region. The first semiconductor region is associated with a first doping type, and the second semiconductor region is associated with a second doping type different from the first doping type. The second semiconductor region is located directly on an insulating layer.

    摘要翻译： 一种用于静电放电保护的半导体器件和方法。 半导体器件包括第一半导体可控整流器和第二半导体可控整流器。 第一半导体可控整流器包括第一半导体区域和第二半导体区域，并且第二半导体可控整流器包括第一半导体区域和第二半导体区域。 第一半导体区域与第一掺杂型相关联，并且第二半导体区域与不同于第一掺杂型的第二掺杂型相关联。 第二半导体区域直接位于绝缘层上。

    Method of detecting the width of lightly doped drain regions
    10.
    发明授权
    Method of detecting the width of lightly doped drain regions 失效
    检测轻掺杂漏极区宽度的方法

    公开(公告)号：US4978627A

    公开(公告)日：1990-12-18

    申请号：US443886

    申请日：1989-11-30

    申请人： Yow-Juang Liu ,  Zahra Hadjizadeh-Amini

    发明人： Yow-Juang Liu ,  Zahra Hadjizadeh-Amini

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6659

    摘要： A process for fabricating field effect transistors with lightly doped drain (LDD) regions having a selected width includes a method of optically detecting the width of spacers used to mask the LDD regions during the source and drain implant and a method of electrically determining (confirming) the width of the LDD regions. In the optical method, reference structures are formed concurrently with the fabrication of the gates for FETs, a spacer material is formed on the substrate, the gates and the reference structures, the spacer material is etched away and the width of the spacers is optically detected by aligning the edges of spacers extending from two reference structures separated by a known distance. In the electrical method, the width is determined by defining a test area with known dimension, forming both N.sup.+ and N.sup.- regions in the test area, measuring the resistance across the test area, calculating the resistance of the N.sup.+ and N.sup.- regions, and calculating the width of the N.sup.- region from the resistance of the N.sup.- region. The electrically determined width is compared with the desired LDD region width, and the difference between the electrically determined width and the desired width is used to adjust the distance between the reference structures for a subsequent processing run.

    摘要翻译： 用于制造具有选定宽度的具有轻掺杂漏极（LDD）区域的场效应晶体管的方法包括在源极和漏极注入期间光学检测用于掩蔽LDD区的间隔物的宽度的方法，以及电确定（确认） LDD区域的宽度。 在光学方法中，与FET的栅极的制造同时形成参考结构，在衬底，栅极和参考结构上形成间隔物材料，蚀刻掉间隔物材料并且光学地检测间隔物的宽度 通过对准由已知距离分开的两个参考结构延伸的间隔件的边缘。 在电气方法中，通过限定具有已知尺寸的测试区域来确定宽度，在测试区域中形成N +和N-区域，测量测试区域上的电阻，计算N +和N-区域的电阻，以及 从N区的电阻计算N-区的宽度。 将电确定的宽度与期望的LDD区域宽度进行比较，并且使用电确定的宽度和期望宽度之间的差来调整用于后续处理运行的参考结构之间的距离。