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公开(公告)号：US20080306723A1
公开(公告)日：2008-12-11
申请号：US12126738
申请日：2008-05-23
CPC分类号： G11C11/005 , G11C13/0004 , G11C13/0033 , G11C14/0045 , G11C14/0063
摘要： An integrated circuit memory device and a method of providing access to multiple memory types within a single integrated circuit memory device are described. In various embodiments, the integrated circuit memory device includes a non-volatile memory array having a first emulated memory region and a second emulated memory region, and a controller having an interface. The memory device is configured to emulate a first emulated memory type and a second emulated memory type. The memory device is further configured to store data in the first emulated memory region when the memory device emulates the first emulated memory type, and in the second emulated memory region when the memory device emulates the second emulated memory type.
摘要翻译： 描述了在单个集成电路存储器件内提供对多种存储器类型的访问的集成电路存储器件和方法。 在各种实施例中，集成电路存储器件包括具有第一仿真存储器区域和第二仿真存储器区域的非易失性存储器阵列，以及具有接口的控制器。 存储器设备被配置为模拟第一仿真存储器类型和第二仿真存储器类型。 存储器设备还被配置为当存储器设备模拟第一仿真存储器类型时，以及当存储器件模拟第二仿真存储器类型时，在第二仿真存储器区域中，将数据存储在第一仿真存储器区域中。
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公开(公告)号：US20050219084A1
公开(公告)日：2005-10-06
申请号：US11089039
申请日：2005-03-25
申请人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier
发明人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： Integrated circuit with a parallel-serial converter The invention relates to an integrated circuit and method for time-offset provision of input data for a parallel-serial converter, in particular for or in a DDR semiconductor memory, having at least n input terminals at which at least n data packets are present in parallel, a delay device arranged in a manner connected downstream of the input terminals, at least some of the data packets present on the input side being output in time-offset fashion with respect to one another by said delay device, a parallel-serial converter arranged in a manner connected downstream of the delay device, which parallel-serial converter performs a conversion of the data packets that are present in parallel and are time-offset with respect to one another into an output data signal comprising the time-offset data packets in serial form, and an output terminal for outputting the output data signal.
摘要翻译： 具有并行串行转换器的集成电路技术领域本发明涉及一种用于时间偏移提供用于并行 - 串行转换器的输入数据的集成电路和方法，特别是用于或在DDR半导体存储器中的至少n个输入端子， 并行存在至少n个数据分组，延迟装置以连接在输入端子下游的方式布置，存在于输入侧的数据分组中的至少一些以相对于彼此的时间偏移方式通过所述 延迟装置，并联串行转换器，以与延迟装置下游相连的方式布置，该并行串行转换器对并行存在的并相对于彼此进行时间偏移的数据包进行转换，并将其转换为输出数据 包括串行形式的时间偏移数据分组的信号和用于输出输出数据信号的输出端。
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公开(公告)号：US06948014B2
公开(公告)日：2005-09-20
申请号：US10396966
申请日：2003-03-25
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C2207/107
摘要： Register for the parallel-serial conversion of data having a plurality of cyclically driven shift registers (2), each comprising series-connected data holding elements (3), each data holding element (3) being connected to a data input line (5), each shift register (2), upon receiving an input control signal (INP) for the shift register (2), loading the data present on the data input lines (5) into the data holding elements (3) connected thereto; each shift register (2), upon receiving an output control signal (OUTP) for the shift register (2), outputting the datum buffer-stored in the last data holding element of the shift register (2), in which case there is connected downstream of each shift register (2) a further data holding element (10), which, upon receiving an input control signal (INP) for loading the preceding shift register (2), is preloaded with the datum for the first data holding element (3-3) of the shift register (2) and, upon reception of the output control signal (OUTP) for the shift register (2), outputs said preloaded datum to an output data line (22) via a data signal driver (18) for generating a serial output data stream with unambiguous data signal states.
摘要翻译： 注册具有多个循环驱动的移位寄存器（2）的数据的并行 - 串行转换，每个包括串联连接的数据保持元件（3），每个数据保持元件（3）连接到数据输入线（5） ，每个移位寄存器（2）在接收到用于移位寄存器（2）的输入控制信号（INP）时，将存在于数据输入线（5）上的数据加载到与其连接的数据保持元件（3）中; 每个移位寄存器（2）在接收到用于移位寄存器（2）的输出控制信号（OUTP）时，输出存储在移位寄存器（2）的最后数据保持元件中的数据缓冲器，在这种情况下， 在每个移位寄存器（2）的下游具有另外的数据保持元件（10），其在接收到用于加载前一移位寄存器（2）的输入控制信号（INP）时，预先加载有用于第一数据保持元件 3），并且在接收到用于移位寄存器（2）的输出控制信号（OUTP）时，经由数据信号驱动器（18）将所述预加载的数据输出到输出数据线（22） ），用于产生具有明确数据信号状态的串行输出数据流。
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公开(公告)号：US07583546B2
公开(公告)日：2009-09-01
申请号：US11855859
申请日：2007-09-14
IPC分类号： G11C7/00
CPC分类号： G11C13/00 , G11C13/0004 , G11C13/0011 , G11C13/0061 , G11C13/0069 , G11C2013/0071 , G11C2013/0076 , G11C2213/79
摘要： The method of operating an integrated circuit including the step of writing to a memory cell, which can assume a first and a second logical state and wherein a change from the second logical state to the first logical state lasts longer than a change from the first logical state to the second logical state, includes reading the logical state of the memory cell, changing, depending on the logical state of the memory cell read, the logical state to the first logical state or retaining the same in the first logical state and, depending on the logical state to be written, changing the logical state to the second logical state or retaining the same in the first logical state.
摘要翻译： 一种操作集成电路的方法，包括写入存储单元的步骤，该存储单元可以采取第一和第二逻辑状态，并且其中从第二逻辑状态到第一逻辑状态的改变比从第一逻辑 状态到第二逻辑状态，包括读取存储器单元的逻辑状态，根据存储单元读取的逻辑状态，将逻辑状态改变到第一逻辑状态或将其保持在第一逻辑状态，并且依赖 在待写入的逻辑状态下，将逻辑状态改变为第二逻辑状态或将其保持在第一逻辑状态。
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公开(公告)号：US07215263B2
公开(公告)日：2007-05-08
申请号：US11089034
申请日：2005-03-25
申请人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier
发明人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： The invention relates to a parallel-serial converter for converting parallel data into serial data, in particular for or in a DDR semiconductor memory, having at least n input terminals at which n data signals are present in parallel, an output terminal for outputting a serial data signal, a controllable latch connected to the input terminals on the input side, a common storage node, which is connected to outputs of the latch and which holds a data signal of the controllable latch present last, a controllable bypass device, which has an input, which is coupled to the storage node on the output side and which has a control terminal, via which a predeterminable state present at the input of the bypass device can be switched onto the storage node. The invention furthermore relates to a semiconductor memory having such a parallel-serial converter and to a method for operating such a parallel-serial converter.
摘要翻译： 本发明涉及一种用于将并行数据转换为串行数据的并行数据转换器，特别是用于或在DDR半导体存储器中，具有并行存在n个数据信号的至少n个输入端，用于输出串行数据的输出端子 数据信号，连接到输入侧的输入端的可控制锁存器，连接到锁存器的输出并保持最后存在的可控制锁存器的数据信号的公共存储节点，可控旁路装置，其具有 输入，其耦合到输出侧的存储节点并且具有控制终端，通过该输入可以将存在于旁路设备的输入端的可预定状态切换到存储节点。 本发明还涉及具有这种并行 - 串行转换器的半导体存储器以及用于操作这种并行 - 串行转换器的方法。
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公开(公告)号：US20050270852A1
公开(公告)日：2005-12-08
申请号：US11136712
申请日：2005-05-25
IPC分类号： G06F3/06 , G11C7/22 , G11C11/4076
CPC分类号： G11C11/4076 , G11C7/1066 , G11C7/20 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C2207/2272
摘要： The invention provides a method for setting and controlling a read latency (L) by means of a FIFO-based read latency control circuit for a read access to a semiconductor memory, having the method steps of providing a common internal clock signal; generating an internal first clock signal and an internal second clock signal, which is different from the first clock signal, from the common clock signal; generating an output pointer for reading out the read data from the first clock signal; generating an input pointer for reading in the read data from the second clock signal; initializing the input and output pointers by allocating a defined, fixedly predetermined time offset between output pointer and input pointer. The invention furthermore provides a corresponding circuit arrangement for carrying out the method.
摘要翻译： 本发明提供了一种用于通过用于对半导体存储器的读取访问的基于FIFO的读延迟控制电路来设置和控制读延迟（L）的方法，具有提供公共内部时钟信号的方法步骤; 从公共时钟信号产生与第一时钟信号不同的内部第一时钟信号和内部第二时钟信号; 产生用于从所述第一时钟信号读出读取数据的输出指针; 生成用于从所述第二时钟信号读取所述读取数据的输入指针; 通过在输出指针和输入指针之间分配定义的，固定地预定的时间偏移来初始化输入和输出指针。 本发明还提供了一种用于执行该方法的相应电路装置。
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公开(公告)号：US06731567B2
公开(公告)日：2004-05-04
申请号：US10350482
申请日：2003-01-24
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1006 , G11C11/4093 , G11C2207/107
摘要： The invention relates to a DDR memory and to a storage method for storing data in a DDR memory having a plurality of memory cells which each have a prescribed word length, in which a serial data input is used to read in serial data on a rising or falling edge of the data clock signal, and a serial-parallel converter is used to put together a prescribed number of data items from the data read in to give a prescribed number of words from data words having the prescribed word length. To make transferring the data from one synchronization area to another synchronization area, and resynchronization thereof, more reliable, the invention involves an interface memory copying the at least one data word from the serial-parallel converter upon receipt of a copy signal which is synchronous with the data block signal and outputting it to a bus upon receipt of an output signal which is synchronous with the system clock signal.
摘要翻译： 本发明涉及DDR存储器和存储方法，用于将数据存储在具有多个存储单元的DDR存储器中，每个存储器单元具有规定的字长，其中使用串行数据输入来读取串行数据上升或 数据时钟信号的下降沿和串行 - 并行转换器用于将从读取的数据中的规定数量的数据项组合在一起，以从具有规定字长的数据字中给出规定数量的字。为了传送 数据从一个同步区域到另一个同步区域，并且其再同步更可靠，本发明涉及一种接收存储器，该接口存储器在接收到与数据块信号同步的复制信号时从串行 - 并行转换器复制至少一个数据字 并在接收到与系统时钟信号同步的输出信号时将其输出到总线。
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公开(公告)号：US06717886B2
公开(公告)日：2004-04-06
申请号：US10248874
申请日：2003-02-26
IPC分类号： G11C800
CPC分类号： G11C7/22 , G11C7/1072 , G11C8/18 , G11C11/4076
摘要： Control circuit for a data path of an S-DRAM which is clocked by a high-frequency clock signal, having a programmable mode register for storing a latency value; a latency generator for temporally delaying a data path control signal, generated by an internal sequence controller, with a switchable latency; a latency decoder, which switches the latency generator in a manner dependent on the latency value stored in the mode register, provision being made of at least one signal delay element, which can be switched in by the latency decoder and serves for the signal delay of the data path control signal with a specific delay time, the latency decoder switching in the associated signal delay element if the stored latency value is high.
摘要翻译： 用于由具有用于存储等待时间值的可编程模式寄存器的由高频时钟信号计时的S-DRAM的数据路径的控制电路; 延迟发生器，用于以可切换的等待时间延迟由内部序列控制器产生的数据路径控制信号; 延迟解码器，其以取决于存储在模式寄存器中的等待时间值的方式切换等待时间发生器，由至少一个信号延迟元件提供，其可由等待时间解码器切换并用于信号延迟 具有特定延迟时间的数据路径控制信号，如果存储的等待时间值高，延迟解码器切换相关联的信号延迟元件。
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9.发明授权Apparatus and method for determining a memory state of a resistive n-level memory cell and memory device 有权用于确定电阻性n级存储器单元和存储器件的存储器状态的装置和方法公开(公告)号：US07876598B2
公开(公告)日：2011-01-25
申请号：US12039633
申请日：2008-02-28
IPC分类号： G11C11/00
CPC分类号： G11C11/5614 , G11C11/5678 , G11C13/0004 , G11C13/0011 , G11C13/004 , G11C13/0061 , G11C27/02 , G11C2013/0054 , G11C2211/5634
摘要： A determination of the memory state of a resistive n-level memory cell is described. The determination includes charging or discharging a read capacity of the memory cell by applying a voltage between a first electrode and a second electrode of the resistive memory cell. A voltage at the second electrode is compared to a reference voltage to obtain a comparison signal. The comparison signal is sampled at, at least, (n−1) time instants during the charge or discharge of the read capacity to obtain sampling values. The memory state of the memory cell can be determined based upon the sampling values.
摘要翻译： 描述了电阻性n级存储单元的存储状态的确定。 确定包括通过在电阻性存储单元的第一电极和第二电极之间施加电压来对存储单元的读取容量进行充电或放电。 将第二电极处的电压与参考电压进行比较以获得比较信号。 在读取容量的充电或放电期间，在至少（n-1）个时刻对比较信号进行采样，以获得采样值。 可以基于采样值来确定存储器单元的存储状态。
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10.发明申请公开(公告)号：US20080304339A1
公开(公告)日：2008-12-11
申请号：US11855859
申请日：2007-09-14
IPC分类号： G11C7/00
CPC分类号： G11C13/00 , G11C13/0004 , G11C13/0011 , G11C13/0061 , G11C13/0069 , G11C2013/0071 , G11C2013/0076 , G11C2213/79
摘要： The method of operating an integrated circuit including the step of writing to a memory cell, which can assume a first and a second logical state and wherein a change from the second logical state to the first logical state lasts longer than a change from the first logical state to the second logical state, includes reading the logical state of the memory cell, changing, depending on the logical state of the memory cell read, the logical state to the first logical state or retaining the same in the first logical state and, depending on the logical state to be written, changing the logical state to the second logical state or retaining the same in the first logical state.
摘要翻译： 一种操作集成电路的方法，包括写入存储单元的步骤，该存储单元可以采取第一和第二逻辑状态，并且其中从第二逻辑状态到第一逻辑状态的改变比从第一逻辑 状态到第二逻辑状态，包括读取存储器单元的逻辑状态，根据存储单元读取的逻辑状态，将逻辑状态改变到第一逻辑状态或将其保持在第一逻辑状态，并且依赖 在待写入的逻辑状态下，将逻辑状态改变为第二逻辑状态或将其保持在第一逻辑状态。
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