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公开(公告)号：US20080306723A1
公开(公告)日：2008-12-11
申请号：US12126738
申请日：2008-05-23
CPC分类号： G11C11/005 , G11C13/0004 , G11C13/0033 , G11C14/0045 , G11C14/0063
摘要： An integrated circuit memory device and a method of providing access to multiple memory types within a single integrated circuit memory device are described. In various embodiments, the integrated circuit memory device includes a non-volatile memory array having a first emulated memory region and a second emulated memory region, and a controller having an interface. The memory device is configured to emulate a first emulated memory type and a second emulated memory type. The memory device is further configured to store data in the first emulated memory region when the memory device emulates the first emulated memory type, and in the second emulated memory region when the memory device emulates the second emulated memory type.
摘要翻译： 描述了在单个集成电路存储器件内提供对多种存储器类型的访问的集成电路存储器件和方法。 在各种实施例中，集成电路存储器件包括具有第一仿真存储器区域和第二仿真存储器区域的非易失性存储器阵列，以及具有接口的控制器。 存储器设备被配置为模拟第一仿真存储器类型和第二仿真存储器类型。 存储器设备还被配置为当存储器设备模拟第一仿真存储器类型时，以及当存储器件模拟第二仿真存储器类型时，在第二仿真存储器区域中，将数据存储在第一仿真存储器区域中。
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公开(公告)号：US20090268532A1
公开(公告)日：2009-10-29
申请号：US12110859
申请日：2008-04-28
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G06F12/0238 , G06F12/0246 , G06F2212/1004 , G06F2212/7202 , G06F2212/7205 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0061 , G11C13/0069 , G11C2213/31 , G11C2213/32
摘要： An integrated circuit includes memory segments, each having at least one memory cell configurable in first and second states to store data, and a controller that controls programming and erasing of the memory segments. The controller maps external memory addresses of write data to internal memory addresses of erased memory segments with no memory cells in the first state such that erased memory segments are programmed with write data. When a write access occurs for an external memory address previously mapped to an internal memory address of a programmed memory segment with at least one memory cell in the first state, the controller remaps the external memory address to another internal memory address of an erased memory segment. The controller identifies programmed memory segments to be erased and controls selective erasure of the identified programmed memory segments, such as programmed memory segments no longer mapped to an external memory address.
摘要翻译： 集成电路包括存储器段，每个存储器段具有可在第一和第二状态下配置以存储数据的至少一个存储单元，以及控制存储器段的编程和擦除的控制器。 控制器将写入数据的外部存储器地址映射到已擦除存储器段的内部存储器地址，而没有存储器单元处于第一状态，使得擦除的存储器段被编写为写入数据。 当对于先前映射到具有处于第一状态的至少一个存储器单元的编程存储器段的内部存储器地址的外部存储器地址进行写访问时，控制器将外部存储器地址重新映射到擦除的存储器段的另一内部存储器地址 。 控制器识别要擦除的已编程存储器段，并且控制所识别的已编程存储器段的选择性擦除，例如不再映射到外部存储器地址的编程存储器段。
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公开(公告)号：US20090268513A1
公开(公告)日：2009-10-29
申请号：US12111774
申请日：2008-04-29
申请人： Luca De Ambroggi , Jan Boris Philipp , Peter Schroegmeier , Gernot Steinlesberger , Christian Pho Duc , Franz Kreupl
发明人： Luca De Ambroggi , Jan Boris Philipp , Peter Schroegmeier , Gernot Steinlesberger , Christian Pho Duc , Franz Kreupl
CPC分类号： G11C13/0069 , G11C11/005 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C2013/0092 , G11C2211/5641 , G11C2213/71 , G11C2213/79
摘要： A memory includes a first memory device including an array of phase changing memory cells. The first memory device is of a first memory type. The integrated circuit includes a second memory device including an array of phase changing memory cells. The second memory device is of a second memory type that is different than the first memory type. The first and second memory devices are packaged together into a single memory device.
摘要翻译： 存储器包括包括相变存储器单元的阵列的第一存储器件。 第一存储器件是第一存储器类型。 集成电路包括包括相变存储器单元的阵列的第二存储器件。 第二存储器件是与第一存储器类型不同的第二存储器类型。 第一和第二存储器件一起封装成单个存储器件。
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公开(公告)号：US07969806B2
公开(公告)日：2011-06-28
申请号：US12110859
申请日：2008-04-28
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G06F12/0238 , G06F12/0246 , G06F2212/1004 , G06F2212/7202 , G06F2212/7205 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0061 , G11C13/0069 , G11C2213/31 , G11C2213/32
摘要： An integrated circuit includes memory segments, each having at least one memory cell configurable in first and second states to store data, and a controller that controls programming and erasing of the memory segments. The controller maps external memory addresses of write data to internal memory addresses of erased memory segments with no memory cells in the first state such that erased memory segments are programmed with write data. When a write access occurs for an external memory address previously mapped to an internal memory address of a programmed memory segment with at least one memory cell in the first state, the controller remaps the external memory address to another internal memory address of an erased memory segment. The controller identifies programmed memory segments to be erased and controls selective erasure of the identified programmed memory segments, such as programmed memory segments no longer mapped to an external memory address.
摘要翻译： 集成电路包括存储器段，每个存储器段具有可在第一和第二状态下配置以存储数据的至少一个存储单元，以及控制存储器段的编程和擦除的控制器。 控制器将写入数据的外部存储器地址映射到已擦除存储器段的内部存储器地址，而没有存储器单元处于第一状态，使得擦除的存储器段被编写为写入数据。 当对于先前映射到具有处于第一状态的至少一个存储器单元的编程存储器段的内部存储器地址的外部存储器地址进行写访问时，控制器将外部存储器地址重新映射到擦除的存储器段的另一内部存储器地址 。 控制器识别要擦除的已编程存储器段，并且控制所识别的已编程存储器段的选择性擦除，例如不再映射到外部存储器地址的编程存储器段。
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公开(公告)号：US20090046499A1
公开(公告)日：2009-02-19
申请号：US12026249
申请日：2008-02-05
申请人： Jan Boris Philipp , Luca De Ambroggi , Peter Schroegmeier , Gernot Steinlesberger , Christian Pho Duc , Franz Kreupl , Thomas Happ
发明人： Jan Boris Philipp , Luca De Ambroggi , Peter Schroegmeier , Gernot Steinlesberger , Christian Pho Duc , Franz Kreupl , Thomas Happ
CPC分类号： G11C13/0069 , G11C7/1006 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0059 , G11C13/0061 , G11C13/0097 , G11C16/3431 , G11C16/349 , G11C2013/0047 , G11C2013/0052 , G11C2013/0092
摘要： An integrated circuit including a memory with an array of memory cells, each memory cell comprising a non-volatile memory element; and a limited read circuit communicatively coupled to the array of memory cells.
摘要翻译： 一种集成电路，包括具有存储器单元阵列的存储器，每个存储器单元包括非易失性存储元件; 以及通信地耦合到存储器单元阵列的有限读取电路。
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6.发明申请Method for accessing a memory cell in an integrated circuit, method of determining a set of word line voltage identifiers in an integrated circuit, method for classifying memory cells in an integrated circuit, method for determining a word line voltage for accessing a memory cell in an integrated circuit and integrated circuits 有权用于访问集成电路中的存储单元的方法，确定集成电路中的一组字线电压标识符的方法，用于对集成电路中的存储单元进行分类的方法，用于确定用于访问存储单元的字线电压的方法 集成电路和集成电路公开(公告)号：US20080253217A1
公开(公告)日：2008-10-16
申请号：US11786765
申请日：2007-04-12
申请人： Andreas Taeuber , Detlev Richter , Luca De Ambroggi , Konrad Seidel , Robert Petter , Marco Ziegelmayer
发明人： Andreas Taeuber , Detlev Richter , Luca De Ambroggi , Konrad Seidel , Robert Petter , Marco Ziegelmayer
CPC分类号： G11C16/08 , G11C11/5614 , G11C11/5664 , G11C11/5678 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/0023 , G11C13/0028 , G11C2213/71
摘要： Embodiments of the invention relate to a method for accessing a memory cell in an integrated circuit, a method of determining a set of word line voltage identifiers in an integrated circuit, a method for classifying memory cells in an integrated circuit, a method for determining a word line voltage for accessing a memory cell in an integrated circuit and integrated circuits. In an embodiment, a method of accessing a memory cell in an integrated circuit, wherein the integrated circuit has a memory cell field including a plurality of memory cells. The method includes selecting a word line voltage identifier from a pre-stored set of word line voltage identifiers, each one of the pre-stored set of word line voltage identifiers being assigned to at least one of the memory cells in the memory cell field and accessing the memory cell using a word line voltage being dependent on the selected word line voltage identifier.
摘要翻译： 本发明的实施例涉及一种用于访问集成电路中的存储单元的方法，确定集成电路中的一组字线电压标识符的方法，用于对集成电路中的存储单元进行分类的方法， 用于访问集成电路中的存储单元的字线电压和集成电路。 在一个实施例中，一种访问集成电路中的存储单元的方法，其中集成电路具有包括多个存储单元的存储单元区域。 该方法包括从预先存储的字线电压标识符组中选择一个字线电压标识符，每一个预先存储的一组字线电压标识符被分配给该存储器单元字段中的至少一个存储单元， 使用取决于所选字线电压标识符的字线电压来访问存储器单元。
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公开(公告)号：US07355908B2
公开(公告)日：2008-04-08
申请号：US10639240
申请日：2003-08-11
申请人： Luca De Ambroggi , Carmelo Condemii
发明人： Luca De Ambroggi , Carmelo Condemii
IPC分类号： G11C7/00
CPC分类号： G11C29/789 , G11C16/344 , G11C29/82
摘要： The nonvolatile storage device is made up of a memory array divided into a plurality of data-storage units and a plurality of redundancy-storage units for replacing respective failed data-storage units. A control unit detects the functionality of the data-storage units and, in case of failure, enables a redundancy-detection unit having a plurality of volatile-memory elements connected through a sequential daisy-chain connection. A nonvolatile memory unit stores, in a nonvolatile way, the redundancy information through a data bus, connected both to the redundancy-detection unit and to the nonvolatile memory unit; in the event of failure, the redundancy-detection unit transfers the addresses of the failed data-storage unit to the nonvolatile memory unit for their nonvolatile storage.
摘要翻译： 非易失性存储装置由划分为多个数据存储单元的存储器阵列和用于替换各个故障数据存储单元的多个冗余存储单元组成。 控制单元检测数据存储单元的功能，并且在故障的情况下，能够实现具有通过连续菊花链连接连接的多个易失性存储元件的冗余检测单元。 非易失性存储器单元通过数据总线以非易失性方式存储冗余信息，数据总线连接到冗余检测单元和非易失性存储器单元; 在故障的情况下，冗余检测单元将非易失性存储单元的故障数据存储单元的地址传送到非易失性存储单元。
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公开(公告)号：US07864593B2
公开(公告)日：2011-01-04
申请号：US11786765
申请日：2007-04-12
申请人： Andreas Taeuber , Detlev Richter , Luca De Ambroggi , Konrad Seidel , Robert Petter , Marco Ziegelmayer
发明人： Andreas Taeuber , Detlev Richter , Luca De Ambroggi , Konrad Seidel , Robert Petter , Marco Ziegelmayer
IPC分类号： G11C16/04
CPC分类号： G11C16/08 , G11C11/5614 , G11C11/5664 , G11C11/5678 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/0023 , G11C13/0028 , G11C2213/71
摘要： A method for classifying memory cells in an integrated circuit is provided, wherein the integrated circuit has a memory cell field including a plurality of memory cells. The method includes determining, for each subset of the memory cells of a plurality of subsets of the memory cells, a threshold voltage distribution; determining whether the determined threshold voltage distributions fulfill a threshold voltage criterion; and depending on whether the determined threshold voltage distributions fulfill the threshold voltage criterion, classifying at least some of the non-selected memory cells.
摘要翻译： 提供了一种用于对集成电路中的存储单元进行分类的方法，其中集成电路具有包括多个存储单元的存储单元场。 该方法包括为存储器单元的多个子集的存储单元的每个子集确定阈值电压分布; 确定所确定的阈值电压分布是否满足阈值电压准则; 并且取决于确定的阈值电压分布是否满足阈值电压准则，对至少一些未选择的存储器单元进行分类。
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公开(公告)号：US06801466B2
公开(公告)日：2004-10-05
申请号：US10331147
申请日：2002-12-27
申请人： Salvatore Giove , Luca De Ambroggi , Salvatore Nicosia , Francesco Tomaiulo , Kumar Promod , Giuseppe Piazza , Francesco Pipitone
发明人： Salvatore Giove , Luca De Ambroggi , Salvatore Nicosia , Francesco Tomaiulo , Kumar Promod , Giuseppe Piazza , Francesco Pipitone
IPC分类号： G11C702
摘要： A circuit for controlling a reference node in a sense amplifier switchable between an operating mode and a stand-by mode is provided. The reference node provides a reference voltage in the operating mode. The circuit may include circuitry for bringing the reference node to a starting voltage upon entry into the stand-by mode, circuitry for keeping the reference node at a pre-charging voltage in the stand-by mode, and circuitry for providing a comparison voltage closer to the pre-charging voltage than the starting voltage. Pulling circuitry may also be included for pulling the reference node toward a power supply voltage. Further, a controller may activate the pulling circuitry upon entering the stand-by mode, and disable the pulling circuitry when the voltage at the reference node reaches the comparison voltage.
摘要翻译： 提供了一种用于控制在操作模式和待机模式之间切换的读出放大器中的参考节点的电路。 参考节点在工作模式下提供参考电压。 电路可以包括用于在进入待机模式时使参考节点进入起始电压的电路，用于将参考节点保持在备用模式下的预充电电压的电路，以及用于提供比较电压更接近的电路 到预充电电压比启动电压。 还可以包括牵引电路以将参考节点拉向电源电压。 此外，控制器可以在进入待机模式时激活拉电路，并且当参考节点处的电压达到比较电压时禁止拉电路。
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