摘要:
This description relates to a method including forming an interlayer dielectric (ILD) layer and a dummy gate structure over a substrate and forming a cavity in a top portion of the ILD layer. The method further includes forming a protective layer to fill the cavity. The method further includes planarizing the protective layer. A top surface of the planarized protective layer is level with a top surface of the dummy gate structure. This description also relates to a semiconductor device including first and second gate structures and an ILD layer formed on a substrate. The semiconductor device further includes a protective layer formed on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, where a top surface of the protective layer is level with the top surfaces of the first and second gate structures.
摘要:
A measurement device is for use with a current-type sensor unit, which, when applied with a driving voltage, is capable of reacting with a target substance for generating a sensor current that corresponds to a concentration level of the target substance, and includes: a driving unit operable to generate the driving voltage that includes alternating current (AC) and direct current (DC) components; and a processing unit for receiving the sensor current from the current-type sensor unit, and operable to determine the concentration level of the target substance according to a peak-to-peak value of the sensor current received by the processing unit.
摘要:
A light emitting system includes: a voltage detecting unit connected across a solid-state light emitting component for detecting a forward voltage thereof and generating a detection voltage having a magnitude dependent on the forward voltage; a current control unit connected to the light emitting component for controlling, according to a compensation voltage, flow of an operating current, which has a magnitude dependent on the compensation voltage, therethrough; and a compensation voltage module connected to the voltage detecting unit and the current control unit, disposed to receive a reference voltage, and configured to generate the compensation voltage, which varies according to the forward voltage, for provision to the current control unit according to the detection voltage, an operating voltage having a magnitude dependent on the operating current, and the reference voltage.
摘要:
Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.
摘要:
A capacitive transimpedance amplifier for a detector unit capable of generating first and second detection currents comprises: a read-out circuit including an integration capacitor coupled between an input node connected to the detector unit, and a common node between first and second transistors connected in series, and a sampling and holding unit coupled between the first common node and an output node for sampling and holding a voltage at the first common node; and a switch unit connected to control ends of the first and second transistors and the input node, and operable between a first state, where the first detection current is read out, and a second state, where the second detection current is read out.
摘要:
A semiconductor device includes a semiconductor substrate; a gate stack overlying the substrate, a spacer formed on sidewalls of the gate stack, and a protection layer overlying the gate stack for filling at least a portion of a space surrounded by the spacer and the top surface of the gate stack. A top surface of the spacer is higher than a top surface of the gate stack.
摘要:
A lighting apparatus includes a light housing, a base mount, an extension member, and a lighting arrangement. The light housing includes a first housing member moveably supported such that the first housing member is capable of rotating about a first longitudinal axis thereof, and a second housing member movably supported such that the second housing member is capable of rotating about a second longitudinal axis thereof. The lighting arrangement is provided in the light housing for forming a plurality of light sources of predetermined intensity, wherein when the first housing member and the second housing member are pivotally moved with respect to each other and rotatably moved about the first longitudinal axis and the second longitudinal axis respectively, the light sources are arranged to selectively and simultaneously provide illumination towards two illumination directions.
摘要:
A lighting apparatus includes a light housing, a base mount, an extension member, and a lighting arrangement. The light housing includes a first housing member moveably supported such that the first housing member is capable of rotating about a first longitudinal axis thereof, and a second housing member movably supported such that the second housing member is capable of rotating about a second longitudinal axis thereof. The lighting arrangement is provided in the light housing for forming a plurality of light sources of predetermined intensity, wherein when the first housing member and the second housing member are pivotally moved with respect to each other and rotatably moved about the first longitudinal axis and the second longitudinal axis respectively, the light sources are arranged to selectively and simultaneously provide illumination towards two illumination directions.
摘要:
This description relates to a gate electrode of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate electrode over the substrate including a first top surface and a sidewall; a source/drain (S/D) region at least partially disposed in the substrate on one side of the gate electrode; a spacer on the sidewall distributed between the gate electrode and the S/D region; and a contact etch stop layer (CESL) adjacent to the spacer and further comprising a portion extending over the S/D region, wherein the portion has a second top surface substantially coplanar with the first top surface.