公开(公告)号：US09263252B2

公开(公告)日：2016-02-16

申请号：US13735949

申请日：2013-01-07

申请人： Chun-Wei Chang ,  Yi-An Lin ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann ,  Yu-Lien Huang

发明人： Chun-Wei Chang ,  Yi-An Lin ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann ,  Yu-Lien Huang

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L21/022 ,  H01L29/66545

摘要： This description relates to a method including forming an interlayer dielectric (ILD) layer and a dummy gate structure over a substrate and forming a cavity in a top portion of the ILD layer. The method further includes forming a protective layer to fill the cavity. The method further includes planarizing the protective layer. A top surface of the planarized protective layer is level with a top surface of the dummy gate structure. This description also relates to a semiconductor device including first and second gate structures and an ILD layer formed on a substrate. The semiconductor device further includes a protective layer formed on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, where a top surface of the protective layer is level with the top surfaces of the first and second gate structures.

摘要翻译： 该描述涉及包括在衬底上形成层间电介质（ILD）层和虚拟栅极结构并在ILD层的顶部形成腔的方法。 该方法还包括形成保护层以填充空腔。 该方法还包括平坦化保护层。 平坦化保护层的顶表面与虚拟栅结构的顶表面平齐。 该描述还涉及包括第一和第二栅极结构以及形成在衬底上的ILD层的半导体器件。 半导体器件还包括形成在ILD层上的保护层，保护层具有与ILD层不同的蚀刻选择性，其中保护层的顶表面与第一和第二栅极结构的顶表面平齐。

公开(公告)号：US09589803B2

公开(公告)日：2017-03-07

申请号：US13572494

申请日：2012-08-10

申请人： Neng-Kuo Chen ,  Clement Hsingjen Wann ,  Yi-An Lin ,  Chun-Wei Chang ,  Sey-Ping Sun

发明人： Neng-Kuo Chen ,  Clement Hsingjen Wann ,  Yi-An Lin ,  Chun-Wei Chang ,  Sey-Ping Sun

IPC分类号： H01L29/94 ,  H01L21/28 ,  H01L21/3105 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L29/66545 ,  H01L21/28123 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： This description relates to a gate electrode of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate electrode over the substrate including a first top surface and a sidewall; a source/drain (S/D) region at least partially disposed in the substrate on one side of the gate electrode; a spacer on the sidewall distributed between the gate electrode and the S/D region; and a contact etch stop layer (CESL) adjacent to the spacer and further comprising a portion extending over the S/D region, wherein the portion has a second top surface substantially coplanar with the first top surface.

摘要翻译： 该描述涉及场效应晶体管的栅电极。 场效应晶体管的示例性结构包括：衬底; 位于所述基板上方的包括第一顶表面和侧壁的栅电极; 至少部分地设置在所述栅电极的一侧的所述衬底中的源极/漏极（S / D）区域; 在所述侧壁上的间隔物分布在所述栅电极和所述S / D区之间; 以及与所述间隔物相邻的接触蚀刻停止层（CESL），并且还包括在所述S / D区域上延伸的部分，其中所述部分具有与所述第一顶表面基本上共面的第二顶表面。

公开(公告)号：US20140061738A1

公开(公告)日：2014-03-06

申请号：US13602494

申请日：2012-09-04

申请人： Chung Chien Wang ,  Yeur-Luen Tu ,  Cheng-Ta Wu ,  Jiech-Fun Lu ,  Chun-Wei Chang ,  Wang-Pen Mo ,  Jhy-Jyi Sze ,  Chia-Shiung Tsai

发明人： Chung Chien Wang ,  Yeur-Luen Tu ,  Cheng-Ta Wu ,  Jiech-Fun Lu ,  Chun-Wei Chang ,  Wang-Pen Mo ,  Jhy-Jyi Sze ,  Chia-Shiung Tsai

IPC分类号： H01L31/0216

CPC分类号： H01L21/266 ,  H01L27/14689

摘要： The present disclosure relates to a method and composition to limit crystalline defects introduced in a semiconductor device during ion implantation. A high-temperature low dosage implant is performed utilizing a tri-layer photoresist which maintains the crystalline structure of the semiconductor device while limiting defect formation within the semiconductor device. The tri-layer photoresist comprises a layer of spin-on carbon deposited onto a substrate, a layer of silicon containing hard-mask formed above the layer of spin-on carbon, and a layer of photoresist formed above the layer of silicon containing hard-mask. A pattern formed in the layer of photoresist is sequentially transferred to the silicon containing hard-mask, then to the spin-on carbon, and defines an area of the substrate to be selectively implanted with ions.

摘要翻译： 本发明涉及在离子注入期间限制在半导体器件中引入的结晶缺陷的方法和组合物。 使用保持半导体器件的晶体结构同时限制半导体器件内的缺陷形成的三层光致抗蚀剂进行高温低剂量注入。 三层光致抗蚀剂包括沉积在基底上的旋涂碳层，在旋涂碳层上方形成的含硅的硬掩模层，以及形成在含硅硬质层的硅层之上的光致抗蚀剂层， 面具。 形成在光致抗蚀剂层上的图案被顺序地转移到含硅的硬掩模，然后转移到旋涂碳上，并且限定要选择性地注入离子的衬底区域。

公开(公告)号：US20130027877A1

公开(公告)日：2013-01-31

申请号：US13553831

申请日：2012-07-20

申请人： Ching-Fu Yang ,  Hui-Lian Chang ,  Ming-Wang Lin ,  Chun-Wei Chang

发明人： Ching-Fu Yang ,  Hui-Lian Chang ,  Ming-Wang Lin ,  Chun-Wei Chang

IPC分类号： H05K7/20

CPC分类号： G06F1/203

摘要： An electronic device including a main body, a rotating base, a motherboard and a driving module is provided. The rotating base has a first vent. The rotating base is pivoted to the main body and suitable for being rotated between an operating position and a retracting position. When the rotating base is located at the operating position, the first vent is exposed from the main body, and when the rotating base is located at the retracting position, the first vent is retracted in the main body. The driving module includes a controlling element and a first locking element. The controlling element is disposed on the main body and suitable for moving between an enable position and a disable position. The first locking element is connected to the controlling element, and the controlling element drives the first locking element to position the rotating base.

摘要翻译： 提供一种包括主体，旋转底座，母板和驱动模块的电子设备。 旋转底座具有第一通气口。 旋转底座枢转到主体并且适于在操作位置和缩回位置之间旋转。 当旋转底座位于操作位置时，第一排气孔从主体露出，当旋转底座位于缩回位置时，第一排气口缩回主体。 驱动模块包括控制元件和第一锁定元件。 控制元件设置在主体上并且适于在使能位置和禁用位置之间移动。 第一锁定元件连接到控制元件，并且控制元件驱动第一锁定元件以定位旋转底座。

公开(公告)号：US20110248394A1

公开(公告)日：2011-10-13

申请号：US13085446

申请日：2011-04-12

申请人： Nan-Jang Chen ,  Chun-Wei Chang ,  Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li ,  Nan-Cheng Chen

发明人： Nan-Jang Chen ,  Chun-Wei Chang ,  Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li ,  Nan-Cheng Chen

IPC分类号： H01L23/495

CPC分类号： H01L24/49 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads disposed along peripheral edges of the die pad; a ground bar between the leads and the die pad; and a plurality of bridges connecting the ground bar with the die pad, wherein a gap between two adjacent bridges has a length that is equal to or less than 3 mm.

摘要翻译： 半导体封装包括管芯焊盘; 安装在管芯焊盘上的半导体管芯; 沿着所述管芯焊盘的周缘设置的多个引线; 引线和芯片焊盘之间的接地棒; 以及将接地棒与管芯焊盘连接的多个桥，其中两个相邻桥之间的间隙具有等于或小于3mm的长度。

公开(公告)号：US07528165B2

公开(公告)日：2009-05-05

申请号：US11195531

申请日：2005-08-01

申请人： Hsing-Pang Hsieh ,  Jing-Ping Liou ,  Jang-Yang Chang ,  Chun-Wei Chang

发明人： Hsing-Pang Hsieh ,  Jing-Ping Liou ,  Jang-Yang Chang ,  Chun-Wei Chang

IPC分类号： A61K31/40

CPC分类号： A61K31/405 ,  C07D209/08 ,  C07D209/12 ,  C07D209/14 ,  C07D209/30 ,  C07D401/06 ,  C07D405/06 ,  C07D491/04

摘要： This invention relates to methods of inhibiting tubulin polymerization and treating cancer and other angiogenesis-related disorders with indole compounds of the formula: wherein L1, L2, R1, R2, Ra, Rb, Rc, Rd, and Re are defined herein.

摘要翻译： 本发明涉及抑制微管蛋白聚合和用下式的吲哚化合物治疗癌症和其它血管发生相关病症的方法：其中L1，L2，R1，R2，Ra，Rb，Rc，Rd和Re在本文中定义。

公开(公告)号：US10919128B2

公开(公告)日：2021-02-16

申请号：US16192771

申请日：2018-11-15

申请人： Chun-Wei Chang

发明人： Chun-Wei Chang

IPC分类号： B25B1/02 ,  B25B1/24

摘要： A modular side-by-side vise structure including a base, a fixture block group located on the base, and a side clamping piece group; the side clamping piece has an upper part and a lower part, and a bolt is screwed in the upper part to prop the lower part, so that the stopper and movable fixture block cling to the base tightly; or the side grooves on both sides of the stopper and movable fixture block are provided with bolt holes, and the inner wall of side clamping piece is provided with a punch hole, the bolt is screwed in the bolt hole through the punch hole, so that the stopper and movable fixture block cling to the base tightly. Therefore, it is unnecessary to hold up the side clamping piece with a hand while tightening or loosening the bolt, favorable for the technician to implement quick assembly or disassembly.

公开(公告)号：US20190152006A1

公开(公告)日：2019-05-23

申请号：US16175841

申请日：2018-10-31

申请人： Chun-Wei Chang

发明人： Chun-Wei Chang

IPC分类号： B23Q3/06

摘要： A fixture block composite structure for workpiece positioning comprises a fixture block group composed of at least a stop fixture block and at least a one-sided movable fixture block. The stop fixture block is fixed to a base by a plurality of mountings, and two opposite lateral sides of the stop fixture block in the extending direction of base are provided with a fixed upright positioning plane respectively. The one-sided movable fixture block has a fixed holder, the holder is fixed to the base by a plurality of mountings. The holder is provided with a movable piece which can be driven to reciprocate towards the positioning plane on the stop fixture block. The movable piece is provided with a clamping surface on one side facing the positioning plane.

公开(公告)号：US08759225B2

公开(公告)日：2014-06-24

申请号：US13602494

申请日：2012-09-04

申请人： Chung Chien Wang ,  Yeur-Luen Tu ,  Cheng-Ta Wu ,  Jiech-Fun Lu ,  Chun-Wei Chang ,  Wang-Pen Mo ,  Jhy-Jyi Sze ,  Chia-Shiung Tsai

发明人： Chung Chien Wang ,  Yeur-Luen Tu ,  Cheng-Ta Wu ,  Jiech-Fun Lu ,  Chun-Wei Chang ,  Wang-Pen Mo ,  Jhy-Jyi Sze ,  Chia-Shiung Tsai

IPC分类号： H01L21/311

CPC分类号： H01L21/266 ,  H01L27/14689

摘要： The present disclosure relates to a method and composition to limit crystalline defects introduced in a semiconductor device during ion implantation. A high-temperature low dosage implant is performed utilizing a tri-layer photoresist which maintains the crystalline structure of the semiconductor device while limiting defect formation within the semiconductor device. The tri-layer photoresist comprises a layer of spin-on carbon deposited onto a substrate, a layer of silicon containing hard-mask formed above the layer of spin-on carbon, and a layer of photoresist formed above the layer of silicon containing hard-mask. A pattern formed in the layer of photoresist is sequentially transferred to the silicon containing hard-mask, then to the spin-on carbon, and defines an area of the substrate to be selectively implanted with ions.

摘要翻译： 本发明涉及在离子注入期间限制在半导体器件中引入的结晶缺陷的方法和组合物。 使用保持半导体器件的晶体结构同时限制半导体器件内的缺陷形成的三层光致抗蚀剂进行高温低剂量注入。 三层光致抗蚀剂包括沉积在基底上的旋涂碳层，在旋涂碳层上方形成的含硅的硬掩模层，以及形成在含硅硬质层的硅层之上的光致抗蚀剂层， 面具。 形成在光致抗蚀剂层上的图案被顺序地转移到含硅的硬掩模，然后转移到旋涂碳上，并且限定要选择性地注入离子的衬底区域。

公开(公告)号：US08379220B2

公开(公告)日：2013-02-19

申请号：US12778363

申请日：2010-05-12

申请人： I-Jen Hsu ,  Chun-Wei Chang

发明人： I-Jen Hsu ,  Chun-Wei Chang

IPC分类号： G01B11/02

CPC分类号： G01B11/2441

摘要： The present invention provides an imaging and measuring apparatus for the surface and the internal interface of an object, which comprises a broadband wave source, a wave-splitting structure, a wave-delaying device, a reflecting component, and a sensor. The broadband wave source transmits a broadband incident wave. The wave-splitting structure splits the broadband incident wave into a first incident beam, a second incident beam, and a third incident beam. The first incident beam is illuminated on an object under test, which reflects a measuring beam. The wave-delaying device receives the second incident beam and reflects a reference beam. The reflecting component receives the third incident beam and reflects a calibration beam. The sensor receives a first interference signal of the measuring beam and the reference beam, and a second interference signal of the reference beam and the calibration beam. By means of the broadband incident wave, the morphologies of the surface and the internal interface of the object can be imaged and measured in a non-destructive way. In addition, by means of the calibration beam, the accuracy of imaging and measuring the surface and the internal interface of the object can be improved.

摘要翻译： 本发明提供一种用于物体的表面和内部界面的成像和测量装置，其包括宽带波源，波分解结构，波延迟装置，反射部件和传感器。 宽带波源传输宽带入射波。 波分解结构将宽带入射波分为第一入射光束，第二入射光束和第三入射光束。 第一个入射光束被照射在被测物体上，反射一个测量光束。 波延迟装置接收第二入射光束并反射参考光束。 反射部件接收第三入射光并反射校准光束。 传感器接收测量光束和参考光束的第一干涉信号，以及参考光束和校准光束的第二干涉信号。 通过宽带入射波，可以以非破坏性的方式对物体的表面和内部界面的形态进行成像和测量。 此外，通过校准光束，可以提高成像和测量物体的表面和内部界面的精度。