公开(公告)号：US20080021692A1

公开(公告)日：2008-01-24

申请号：US11459060

申请日：2006-07-21

申请人： Rajat Chaudhry ,  Sang H. Dhong ,  Gilles Gervais ,  Danny J. Klema

发明人： Rajat Chaudhry ,  Sang H. Dhong ,  Gilles Gervais ,  Danny J. Klema

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F1/3203 ,  G06F2217/78 ,  Y02D10/124

摘要： A power estimation system uses a hardware accelerated simulator to advance simulation to a point of interest for power estimation. The hardware accelerated simulator generates a checkpoint file, which is then used by a software simulator to initiate simulation of the processor design model for power estimation. An on-the-fly power estimator provides power calculations in memory. Thus, the power estimation system described herein isolates instruction sequences to determine portions of software code that may consume excess power or generate noise and to provide a more accurate power estimate on the fly.

摘要翻译： 功率估计系统使用硬件加速模拟器将模拟推进到功率估计的兴趣点。 硬件加速模拟器产生一个检查点文件，然后由软件模拟器用来启动用于功率估计的处理器设计模型的仿真。 动态功率估计器在存储器中提供功率计算。 因此，本文描述的功率估计系统隔离指令序列以确定可消耗过多功率或产生噪声的软件代码的部分并且在飞行中提供更准确的功率估计。

公开(公告)号：US07610531B2

公开(公告)日：2009-10-27

申请号：US11531287

申请日：2006-09-13

申请人： Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Brad W. Michael ,  Mack W. Riley

发明人： Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Brad W. Michael ,  Mack W. Riley

IPC分类号： G01R31/28

CPC分类号： G01R31/318536 ,  G01R31/318575

摘要： Mechanisms for modifying a test pattern to control power supply noise are provided. A portion of a sequence of states in a test sequence of a test pattern waveform is modified so as to achieve a circuit voltage, e.g., an on-chip voltage, which approximates a nominal circuit voltage, such as produced by the application of other portions of the sequence of states in the same or different test sequences. For example, hold state cycles or shift-scan state cycles may be inserted or removed prior to test state cycles in the test pattern waveform. The insertion/removal shifts the occurrence of the test state cycles within the test pattern waveform so as to adjust the voltage response of the test state cycles so that they more closely approximate a nominal voltage response. In this way, false failures due to noise in the voltage supply may be eliminated.

摘要翻译： 提供了修改测试模式以控制电源噪声的机制。 修改测试图形波形的测试序列中的状态序列的一部分被修改，以便实现近似标称电路电压的电路电压，例如片上电压，例如通过施加其它部分产生的电压 的相同或不同测试序列中的状态序列。 例如，保持状态周期或移位扫描状态周期可以在测试模式波形中的测试状态周期之前被插入或移除。 插入/移除将测试状态周期的发生移动到测试图形波形内，以便调整测试状态周期的电压响应，使得它们更接近于额定电压响应。 以这种方式，可以消除由于电压源中的噪声引起的错误故障。

公开(公告)号：US20080168318A1

公开(公告)日：2008-07-10

申请号：US11621766

申请日：2007-01-10

申请人： Jonathan J. DeMent ,  Sang H. Dhong ,  Gilles Gervais ,  Alain Loiseau ,  Kirk D. Peterson ,  John L. Sinchak

发明人： Jonathan J. DeMent ,  Sang H. Dhong ,  Gilles Gervais ,  Alain Loiseau ,  Kirk D. Peterson ,  John L. Sinchak

IPC分类号： G01R31/30 ,  G06F11/00

CPC分类号： G01R31/3004 ,  G01R31/31721 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A voltage identifier (VID) sorting system is provided that optimizes processor power and operating voltage guardband at a constant processor frequency. The VID sorting system determines a voltage versus current curve for the processor. The VID sorting system then uses the voltage versus current characteristics to calculate the power for each VID to determine an acceptable range of VIDs within the maximum power criteria. The VID sorting system then tests VIDs in the range and selects a VID from the range to optimize for minimum power and/or maximum voltage guardband at a constant processor frequency.

摘要翻译： 提供了一种电压标识符（VID）分类系统，其以恒定的处理器频率优化处理器功率和工作电压保护带。 VID分选系统确定处理器的电压与电流曲线。 然后，VID分选系统使用电压与电流特性来计算每个VID的功率，以确定最大功率标准内的VID的可接受范围。 VID分类系统然后测试该范围内的VID，并从该范围中选择一个VID，以在恒定的处理器频率下对最小功率和/或最大电压保护带进行优化。

公开(公告)号：US07739573B2

公开(公告)日：2010-06-15

申请号：US11621766

申请日：2007-01-10

申请人： Jonathan J. DeMent ,  Sang H. Dhong ,  Gilles Gervais ,  Alain Loiseau ,  Kirk D. Peterson ,  John L. Sinchak

发明人： Jonathan J. DeMent ,  Sang H. Dhong ,  Gilles Gervais ,  Alain Loiseau ,  Kirk D. Peterson ,  John L. Sinchak

IPC分类号： G01R31/30

CPC分类号： G01R31/3004 ,  G01R31/31721 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A voltage identifier (VID) sorting system is provided that optimizes processor power and operating voltage guardband at a constant processor frequency. The VID sorting system determines a voltage versus current curve for the processor. The VID sorting system then uses the voltage versus current characteristics to calculate the power for each VID to determine an acceptable range of VIDs within the maximum power criteria. The VID sorting system then tests VIDs in the range and selects a VID from the range to optimize for minimum power and/or maximum voltage guardband at a constant processor frequency.

摘要翻译： 提供了一种电压标识符（VID）分类系统，其以恒定的处理器频率优化处理器功率和工作电压保护带。 VID分选系统确定处理器的电压与电流曲线。 然后，VID分选系统使用电压与电流特性来计算每个VID的功率，以确定最大功率标准内的VID的可接受范围。 VID分类系统然后测试该范围内的VID，并从该范围中选择一个VID，以在恒定的处理器频率下对最小功率和/或最大电压保护带进行优化。

公开(公告)号：US20090112550A1

公开(公告)日：2009-04-30

申请号：US11927840

申请日：2007-10-30

申请人： Makoto Aikawa ,  Jonathan J. DeMent ,  Sang H. Dhong ,  Brian K. Flachs ,  Gilles Gervais ,  Iwao Takiguchi ,  Tetsuji Tamura

发明人： Makoto Aikawa ,  Jonathan J. DeMent ,  Sang H. Dhong ,  Brian K. Flachs ,  Gilles Gervais ,  Iwao Takiguchi ,  Tetsuji Tamura

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G01R31/318364

摘要： A system and method for generating a worst case current waveform for testing of integrated circuit devices are provided. Architectural analysis of an integrated circuit device is first performed to determine an initial worst case power workload to be applied to the integrated circuit device. Thereafter, the derived worst case power workload is applied to a model and is simulated to generate a worst case current waveform that is input to an electrical model of the integrated circuit device to generate a worst case noise budget value. The worst case noise budget value is then compared to measured noise from application of the worst case power workload to a hardware implemented integrated circuit device. The worst case current waveform may be selected for future testing of integrated circuit devices or modifications to the simulation models may be performed and the process repeated based on the results of the comparison.

摘要翻译： 提供一种用于产生用于集成电路器件测试的最坏情况电流波形的系统和方法。 首先执行集成电路装置的结构分析，以确定要应用于集成电路装置的初始最坏情况功率工作负荷。 此后，将得到的最坏情况功率工作量应用于模型，并且被模拟以产生输入到集成电路器件的电气模型以产生最坏情况噪声预算值的最坏情况电流波形。 然后将最坏情况的噪声预算值与从最坏情况功率工作负载应用于硬件实现的集成电路设备的测量噪声进行比较。 可以选择最坏情况下的电流波形以用于集成电路设备的未来测试，或者可以对仿真模型进行修改，并且基于比较的结果重复该过程。

公开(公告)号：US20080189090A1

公开(公告)日：2008-08-07

申请号：US11671852

申请日：2007-02-06

申请人： Makoto Aikawa ,  Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Yoichi Nishino ,  Iwao Takiguchi ,  Tetsuji Tamura ,  Yaping Zhou

发明人： Makoto Aikawa ,  Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Yoichi Nishino ,  Iwao Takiguchi ,  Tetsuji Tamura ,  Yaping Zhou

IPC分类号： G06G7/62 ,  G06F17/50

CPC分类号： G06F17/5036 ,  G01R31/318357

摘要： A system and method for determining a guard band for an operating voltage of an integrated circuit device are provided. The system and method provide a mechanism for calculating the guard band based on a comparison of simulated noise obtained from a simulation of the integrated circuit device using a worst case waveform stimuli with simulated or measured power supply noise of a workload/test pattern that may be achieved using testing equipment. A scaling factor for the guard band is determined by comparing results of a simulation of a workload/test pattern with measured results of the workload/test pattern as applied to a hardware implementation of the integrated circuit device. This scaling factor is applied to a difference between the noise generated through simulation of the workload/test pattern and the noise generated through simulation of the worst case current waveform to generate a guard band value.

摘要翻译： 提供了一种用于确定集成电路装置的工作电压的保护带的系统和方法。 该系统和方法提供了一种基于使用最差情况波形刺激从集成电路装置的模拟获得的模拟噪声与可能是工作负载/测试模式的模拟或测量的电源噪声的比较来计算保护频带的机制 使用测试设备实现。 通过将工作负载/测试模式的仿真结果与应用于集成电路设备的硬件实现的工作负载/测试模式的测量结果进行比较来确定保护频带的缩放因子。 该缩放因子被应用于通过模拟工作负载/测试模式产生的噪声与通过模拟最坏情况电流波形产生的噪声之间的差异以产生保护带值。

公开(公告)号：US20110252260A1

公开(公告)日：2011-10-13

申请号：US12756570

申请日：2010-04-08

申请人： Brian K. Flachs ,  Gilles Gervais ,  Sang H. Dhong ,  Tetsuji Tamura

发明人： Brian K. Flachs ,  Gilles Gervais ,  Sang H. Dhong ,  Tetsuji Tamura

IPC分类号： G06F1/00

CPC分类号： G06F9/5094 ,  G06F1/3287 ,  G06F1/329 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24 ,  Y02D50/20

摘要： A mechanism is provided for reducing power consumed by a multi-core processor. Responsive to a number of properly functioning processor cores being more than a required number of processor cores in a multi-core processor, the power consumption measurement module determines a number of the properly functioning processor cores to disable. The power consumption measurement module initiates an equal amount of workload to be processed by each of the properly functioning processor cores. The power consumption measurement module determines power consumed by each of the properly functioning processor cores. The power consumption measurement module deactivates one or more of the properly functioning processor cores that have maximum power in order that the number of properly functioning processor cores deactivated is equal to the number of properly functioning processor cores to disable.

摘要翻译： 提供了用于减少多核处理器消耗的功率的机制。 响应于多个正常运行的处理器内核超过多核处理器中所需数量的处理器内核，功耗测量模块确定要禁用的正常运行的处理器内核的数量。 功耗测量模块启动要由每个正常运行的处理器内核处理的相同数量的工作负载。 功耗测量模块确定每个正常运行的处理器内核消耗的功耗。 功耗测量模块取消激活具有最大功率的一个或多个正常运行的处理器内核，以使已正常运行的处理器内核的数量等于要禁用的正常运行的处理器内核的数量。

公开(公告)号：US07917347B2

公开(公告)日：2011-03-29

申请号：US11927840

申请日：2007-10-30

申请人： Makoto Aikawa ,  Jonathan J. DeMent ,  Sang H. Dhong ,  Brian K. Flachs ,  Gilles Gervais ,  Iwao Takiguchi ,  Tetsuji Tamura

发明人： Makoto Aikawa ,  Jonathan J. DeMent ,  Sang H. Dhong ,  Brian K. Flachs ,  Gilles Gervais ,  Iwao Takiguchi ,  Tetsuji Tamura

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G01R31/318364

摘要： Mechanisms for generating a worst case current waveform for testing of integrated circuit devices are provided. Architectural analysis of an integrated circuit device is first performed to determine an initial worst case power workload to be applied to the integrated circuit device. Thereafter, the derived worst case power workload is applied to a model and is simulated to generate a worst case current waveform that is input to an electrical model of the integrated circuit device to generate a worst case noise budget value. The worst case noise budget value is then compared to measured noise from application of the worst case power workload to a hardware implemented integrated circuit device. The worst case current waveform may be selected for future testing of integrated circuit devices or modifications to the simulation models may be performed and the process repeated based on the results of the comparison.

摘要翻译： 提供了用于产生用于集成电路器件测试的最坏情况电流波形的机构。 首先执行集成电路装置的结构分析，以确定要应用于集成电路装置的初始最坏情况功率工作负荷。 此后，将得到的最坏情况功率工作量应用于模型，并且被模拟以产生输入到集成电路器件的电气模型以产生最坏情况噪声预算值的最坏情况电流波形。 然后将最坏情况的噪声预算值与从最坏情况功率工作负载应用于硬件实现的集成电路设备的测量噪声进行比较。 可以选择最坏情况下的电流波形以用于集成电路设备的未来测试，或者可以对仿真模型进行修改，并且基于比较的结果重复该过程。

公开(公告)号：US07447602B1

公开(公告)日：2008-11-04

申请号：US11758034

申请日：2007-06-05

申请人： Douglas H. Bradley ,  Jonathan J. DeMent ,  Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Yoichi Nishino

发明人： Douglas H. Bradley ,  Jonathan J. DeMent ,  Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Yoichi Nishino

IPC分类号： G01R21/00 ,  G01R21/06

CPC分类号： G01R31/31721 ,  G01R31/31718

摘要： A system and method for sorting processor chips based on a thermal design point are provided. With the system and method, for each processor chip, a high power workload is run on the processor chip to determine a voltage regulator module (VRM) load line. Thereafter, a thermal design point (TDP) workload is applied to the processor chip and the voltage is varied until a performance of the processor chip falls on the VRM load line. At this point, the power input to the processor chip is measured and used to sort, or bin, the processor chip. The various workloads applied have a constant frequency. From this sorting of processor chips, high speed processors that require less voltage to achieve a desired frequency and low current processors that drain less current while running at a desired frequency may be identified.

摘要翻译： 提供了一种基于热设计点分类处理器芯片的系统和方法。 利用系统和方法，对于每个处理器芯片，在处理器芯片上运行高功率工作负载以确定电压调节器模块（VRM）负载线。 此后，将热设计点（TDP）工作量应用于处理器芯片，并且改变电压直到处理器芯片的性能落在VRM负载线上。 此时，对处理器芯片的电源输入进行测量并用于对处理器芯片进行排序或分页。 应用的各种工作负载具有恒定的频率。 从处理器芯片的这种排序中，可以识别需要较少电压以实现期望频率的低速处理器和在期望频率下运行时消耗较少电流的低电流处理器。

公开(公告)号：US08381006B2

公开(公告)日：2013-02-19

申请号：US12756570

申请日：2010-04-08

申请人： Brian K. Flachs ,  Gilles Gervais ,  Sang H. Dhong ,  Tetsuji Tamura

发明人： Brian K. Flachs ,  Gilles Gervais ,  Sang H. Dhong ,  Tetsuji Tamura

IPC分类号： G06F1/00

CPC分类号： G06F9/5094 ,  G06F1/3287 ,  G06F1/329 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24 ,  Y02D50/20

摘要： A mechanism is provided for reducing power consumed by a multi-core processor. Responsive to a number of properly functioning processor cores being more than a required number of processor cores in a multi-core processor, the power consumption measurement module determines a number of the properly functioning processor cores to disable. The power consumption measurement module initiates an equal amount of workload to be processed by each of the properly functioning processor cores. The power consumption measurement module determines power consumed by each of the properly functioning processor cores. The power consumption measurement module deactivates one or more of the properly functioning processor cores that have maximum power in order that the number of properly functioning processor cores deactivated is equal to the number of properly functioning processor cores to disable.

摘要翻译： 提供了用于减少多核处理器消耗的功率的机制。 响应于多个正常运行的处理器内核超过多核处理器中所需数量的处理器内核，功耗测量模块确定要禁用的正常运行的处理器内核的数量。 功耗测量模块启动要由每个正常运行的处理器内核处理的相同数量的工作负载。 功耗测量模块确定每个正常运行的处理器内核消耗的功耗。 功耗测量模块取消激活具有最大功率的一个或多个正常运行的处理器内核，以使已正常运行的处理器内核的数量等于要禁用的正常运行的处理器内核的数量。