公开(公告)号：US07833839B1

公开(公告)日：2010-11-16

申请号：US11856033

申请日：2007-09-15

Applicant: Maxat Touzelbaev ,  Raj Master ,  Frank Kuechenmeister

Inventor： Maxat Touzelbaev ,  Raj Master ,  Frank Kuechenmeister

IPC: H01L21/00

CPC classification number: H01L23/42 ,  H01L23/433 ,  H01L24/27 ,  H01L24/28 ,  H01L24/31 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Various methods and apparatus for establishing a thermal pathway for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes placing a gel-type thermal interface material in a preselected pattern on a semiconductor chip that is coupled to a substrate. The preselected pattern of gel-type thermal interface material is allowed to partially set up. Additional thermal interface material is placed on the semiconductor chip and cured.

Abstract translation: 公开了用于建立半导体器件的热通路的各种方法和装置。 在一个方面，提供了一种制造方法，其包括将凝胶型热界面材料以耦合到衬底的半导体芯片上的预选图案放置。 允许凝胶型热界面材料的预选图案部分地设置。 另外的热界面材料放置在半导体芯片上并固化。

公开(公告)号：US20090057877A1

公开(公告)日：2009-03-05

申请号：US11846618

申请日：2007-08-29

Applicant: Maxat Touzelbaev ,  Raj Master ,  Frank Kuechenmeister

Inventor： Maxat Touzelbaev ,  Raj Master ,  Frank Kuechenmeister

IPC: H01L23/34 ,  H01L21/00

CPC classification number: H01L23/3737 ,  H01L21/50 ,  H01L23/3735 ,  H01L23/42 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Various methods and apparatus for establishing a thermal pathway for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes forming a metal layer on a semiconductor chip and forming a gel-type thermal interface material layer on the metal layer. A solvent and a catalyst material are applied to the metal layer prior to forming the gel-type thermal interface material layer to facilitate bonding between the gel-type thermal interface material layer and the metal layer.

Abstract translation: 公开了用于建立半导体器件的热通路的各种方法和装置。 一方面，提供了一种制造方法，包括在半导体芯片上形成金属层，并在金属层上形成凝胶型热界面材料层。 在形成凝胶型热界面材料层之前，将溶剂和催化剂材料施加到金属层，以促进凝胶型热界面材料层和金属层之间的结合。

公开(公告)号：US07678615B2

公开(公告)日：2010-03-16

申请号：US11846618

申请日：2007-08-29

Applicant: Maxat Touzelbaev ,  Raj Master ,  Frank Kuechenmeister

Inventor： Maxat Touzelbaev ,  Raj Master ,  Frank Kuechenmeister

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/34 ,  H01L23/10 ,  H01L23/12

CPC classification number: H01L23/3737 ,  H01L21/50 ,  H01L23/3735 ,  H01L23/42 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Various methods and apparatus for establishing a thermal pathway for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes forming a metal layer on a semiconductor chip and forming a gel-type thermal interface material layer on the metal layer. A solvent and a catalyst material are applied to the metal layer prior to forming the gel-type thermal interface material layer to facilitate bonding between the gel-type thermal interface material layer and the metal layer.

Abstract translation: 公开了用于建立半导体器件的热通路的各种方法和装置。 一方面，提供了一种制造方法，包括在半导体芯片上形成金属层，并在金属层上形成凝胶型热界面材料层。 在形成凝胶型热界面材料层之前，将溶剂和催化剂材料施加到金属层，以促进凝胶型热界面材料层和金属层之间的结合。

公开(公告)号：US06657707B1

公开(公告)日：2003-12-02

申请号：US09624493

申请日：2000-07-24

Applicant: David Bruce Morken ,  Raj Master

Inventor： David Bruce Morken ,  Raj Master

IPC: G01N100

CPC classification number: H01L24/81 ,  H01L24/75 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/13006 ,  H01L2224/13111 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/0269 ,  H05K3/3457 ,  H01L2224/05541 ,  H01L2224/05005

Abstract: Raised electrical contacts, such as Pb-alloy solder bumps or balls utilized in semiconductor IC flip-chip devices, are selectively and readily removed from underlying contact pads by means of a chemical etching process, thereby facilitating metallurgical and/or microstructural inspection and/or analysis of the contact pads for failure analysis, void formation, electromigration, diffusion, loss of adhesion, etc., by a variety of optical and microscopic techniques.

Abstract translation: 通过化学蚀刻工艺，可以选择性地并且容易地从下面的接触焊盘去除诸如用于半导体IC倒装芯片的Pb合金焊料凸起或球的升高的电触点，从而有助于冶金和/或微结构检查和/或 通过各种光学和微观技术分析用于故障分析，空隙形成，电迁移，扩散，粘附丧失等的接触垫。

公开(公告)号：US20060289977A1

公开(公告)日：2006-12-28

申请号：US11167425

申请日：2005-06-27

Applicant: Raj Master ,  Srinivasan Anand ,  Srinivasan Parthasarathy ,  Yew Mui

Inventor： Raj Master ,  Srinivasan Anand ,  Srinivasan Parthasarathy ,  Yew Mui

IPC: H01L23/02

CPC classification number: C22C13/02 ,  B23K35/262 ,  H01L23/49811 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/19105 ,  H05K3/3463 ,  H05K2201/10318 ,  H05K2201/10674 ,  H05K2203/047 ,  H01L2224/81 ,  H01L2224/0401

Abstract: A package substrate includes die solder pads and pin solder fillets. The pin solder fillets might comprise between approximately 90 wt % to approximately 99 wt % tin and approximately 10 wt % to 1 wt % antimony. The die solder pads might comprise between approximately 4 wt % to approximately 8 wt % bismuth, approximately 2 wt % to approximately 4 wt % silver, approximately 0 wt % to approximately 0.7 wt % copper, and approximately 87 wt % to approximately 92 wt % tin. The die solder pads might comprise between approximately 7 wt % to approximately 20 wt % indium, between approximately 2 wt % to approximately 4.5 wt % silver, between approximately 0 wt % to approximately 0.7 wt % copper, between approximately 0 wt % to approximately 0.5 wt % antimony, and between approximately 74.3 wt % to approximately 90 wt % tin.

Abstract translation: 封装衬底包括管芯焊盘和焊脚焊脚。 针焊料焊片可以包含约90重量％至约99重量％的锡和约10重量％至1重量％的锑。 模焊盘可以包括约4重量％至约8重量％的铋，约2重量％至约4重量％的银，约0重量％至约0.7重量％的铜，以及约87重量％至约92重量％ 锡。 模焊盘可以包括约7重量％至约20重量％的铟，约2重量％至约4.5重量％的银之间，约0重量％至约0.7重量％的铜之间，约0重量％至约0.5重量％ 重量锑，以及约74.3重量％至约90重量％的锡。