公开(公告)号：US06406926B1

公开(公告)日：2002-06-18

申请号：US09930241

申请日：2001-08-15

Applicant: Shawn M. O'Rourke ,  Ravichandran Subrahmanyan

Inventor： Shawn M. O'Rourke ,  Ravichandran Subrahmanyan

IPC: H01L2100

CPC classification number: B82Y10/00 ,  H01J9/025 ,  H01J2201/30469

Abstract: A vacuum microelectronic device (10,40) is formed by applying a first conductor (13,14) to a substrate (11) and utilizing the first conductor (13,14) to expose a dielectric material (18) and a second conductive material (19) from a back surface of the substrate (11). A second conductor (29) and a dielectric (28) are formed from the second conductive material (19) and the dielectric material (18), respectively. This method self-aligns the dielectric (28) and the second conductor (29) with the first conductor (13,14). Electron emitters (31,33) of the vacuum microelectronic device (10,40) are formed on the first conductor (13,14).

Abstract translation: 通过将第一导体（13,14）施加到衬底（11）并利用第一导体（13,14）暴露电介质材料（18）和第二导电材料（18）形成真空微电子器件（10,40） （19）从所述基板（11）的背面延伸。 第二导体（29）和电介质（28）分别由第二导电材料（19）和电介质材料（18）形成。 该方法使电介质（28）和第二导体（29）与第一导体（13,14）自对准。 真空微电子器件（10,40）的电子发射体（31,33）形成在第一导体（13,14）上。

公开(公告)号：US06902658B2

公开(公告)日：2005-06-07

申请号：US10024164

申请日：2001-12-18

Applicant: Albert Alec Talin ,  Kenneth Andrew Dean ,  Shawn M. O'Rourke ,  Bernard F. Coll ,  Matthew Stainer ,  Ravichandran Subrahmanyan

Inventor： Albert Alec Talin ,  Kenneth Andrew Dean ,  Shawn M. O'Rourke ,  Bernard F. Coll ,  Matthew Stainer ,  Ravichandran Subrahmanyan

IPC: H01J1/304 ,  H01J9/02 ,  C25D13/12

CPC classification number: C25D13/02 ,  B82Y10/00 ,  B82Y30/00 ,  H01J1/3042 ,  H01J9/025

Abstract: A method of fabricating a field emission device cathode using electrophoretic deposition of carbon nanotubes in which a separate step of depositing a binder material onto a substrate, is performed prior to carbon nanotube particle deposition. First, a binder layer is deposited on a substrate from a solution containing a binder material. The substrate having the binder material deposited thereon is then transferred into a carbon nanotube suspension bath allowing for coating of the carbon nanotube particles onto the substrate. Thermal processing of the coating transforms the binder layer properties which provides for the adhesion of the carbon nanotube particles to the binder material.

Abstract translation: 在碳纳米管颗粒沉积之前进行使用碳纳米管的电泳沉积来制造场发射器件阴极的方法，其中在衬底上沉积粘合剂材料的单独步骤。 首先，将粘合剂层从含有粘合剂材料的溶液沉积在基材上。 然后将其上沉积有粘合剂材料的基材转移到允许将碳纳米管颗粒涂覆到基材上的碳纳米管悬浮液浴中。 涂层的热处理改变粘合剂层性质，其提供了将碳纳米管颗粒粘附到粘合剂材料上。

公开(公告)号：US5587342A

公开(公告)日：1996-12-24

申请号：US415972

申请日：1995-04-03

Applicant: Jong-Kai Lin ,  William H. Lytle ,  Ravichandran Subrahmanyan

Inventor： Jong-Kai Lin ,  William H. Lytle ,  Ravichandran Subrahmanyan

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14

Abstract: Interconnect bumps are formed on a circuit substrate using printing or dispensing techniques with a wet photoresist layer as a mask. A conductive paste is disposed in openings of a wet photoresist layer. The conductive paste is at least partially cured before the wet photoresist layer is removed. Alternatively, the wet photoresist layer may remain if it is a photo-imagable polyimide.

Abstract translation: 使用具有湿光致抗蚀剂层作为掩模的印刷或分配技术在电路基板上形成互连凸点。 将导电浆料设置在湿光致抗蚀剂层的开口中。 在去除湿光致抗蚀剂层之前，导电浆料至少部分固化。 或者，如果湿光致抗蚀剂层是可光成像的聚酰亚胺，则可保留湿光致抗蚀剂层。

公开(公告)号：US5411400A

公开(公告)日：1995-05-02

申请号：US209353

申请日：1994-03-14

Applicant: Ravichandran Subrahmanyan ,  Ravinder K. Sharma ,  William H. Lytle ,  Barry C. Johnson

Inventor： Ravichandran Subrahmanyan ,  Ravinder K. Sharma ,  William H. Lytle ,  Barry C. Johnson

IPC: H05K3/32 ,  H05K7/10 ,  H01R9/09

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/90 ,  H05K3/326 ,  H05K7/1053 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13147 ,  H01L2224/81136 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81899 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14

Abstract: A plurality of inserts (12) formed on a first substrate (11). A plurality of sockets (14) formed on a second substrate (13). Each socket of the plurality of sockets (14) on the second substrate (13) has a corresponding insert from the plurality of inserts (12) which physically aligns for coupling. At least one of the first (11) or second (13) substrates must be a semiconductor substrate. This arrangement allows for electrically connecting a semiconductor device or structure to another device for testing, burn-in, or final assembly.

Abstract translation: 形成在第一基板（11）上的多个插入件（12）。 形成在第二基板（13）上的多个插座（14）。 第二基板（13）上的多个插座（14）中的每个插座具有与多个插入件（12）相对应的插入物，物理上对准用于联接。 第一（11）或第二（13）衬底中的至少一个衬底必须是半导体衬底。 这种布置允许将半导体器件或结构电连接到另一个用于测试，老化或最终组装的器件。

公开(公告)号：US5346857A

公开(公告)日：1994-09-13

申请号：US952005

申请日：1992-09-28

Applicant: Thomas A. Scharr ,  Russell T. Lee ,  Ravichandran Subrahmanyan

Inventor： Thomas A. Scharr ,  Russell T. Lee ,  Ravichandran Subrahmanyan

IPC: H01L21/60 ,  H01L21/283 ,  H01L21/58 ,  H01L21/603

CPC classification number: H01L24/81 ,  H01L24/75 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/75 ,  H01L2224/75283 ,  H01L2224/8123 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14

Abstract: A method for flip-chip bonding an integrated circuit die to a substrate. A substrate (21) having conductive bonding areas (22) coated with tin (23) is secured to a bottom end effector of a flip-chip bonding apparatus. An integrated circuit die (26) having gold bumps (28) is secured to a die tool of the flip-chip bonding apparatus. A gold-tin eutectic bond is formed between the integrated circuit die (26) and the conductive bonding areas (22) of the substrate (21).

Abstract translation: 一种用于将集成电路管芯倒装连接到衬底的方法。 具有涂覆有锡（23）的导电接合区域（22）的基板（21）固定到倒装芯片接合装置的底端执行器。 具有金凸块（28）的集成电路芯片（26）固定到倒装芯片接合装置的模具工具。 在集成电路管芯（26）和衬底（21）的导电接合区域（22）之间形成金锡共晶键。