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1.发明授权Method and system for power-efficient and non-signal-degrading voltage regulation in memory subsystems 有权存储器子系统中功率效率和非信号降解电压调节的方法和系统公开(公告)号：US08782452B2
公开(公告)日：2014-07-15
申请号：US13383359
申请日：2009-07-27
CPC分类号： G11C5/04 , G06F1/3225 , G11C5/147
摘要： Embodiments of the present invention are directed to a memory subsystem comprising a memory controller, multiple memory modules interconnected with the memory controller by one or more communications media, each memory module comprising a substrate to which multiple memory chips are mounted and electronically connected to the communications media, and a power-supply signal routed to two or more voltage regulators within the memory subsystem from a system power supply, the voltage regulators outputting two or more internal power signals, each power signal providing a different, regulated voltage, which are routed to each of the memory chips. Another embodiment of the present invention is directed to a memory module comprising a substrate to which multiple memory chips are mounted and two or more voltage regulators mounted to, or fabricated within, the substrate.
摘要翻译： 本发明的实施例涉及一种存储器子系统，包括存储器控制器，通过一个或多个通信介质与存储器控制器互连的多个存储器模块，每个存储器模块包括衬底，多个存储器芯片被安装到该衬底上并且电连接到通信 介质和从系统电源路由到存储器子系统内的两个或更多个稳压器的电源信号，电压调节器输出两个或更多个内部功率信号，每个功率信号提供不同的调节电压，其被路由到 每个内存芯片。 本发明的另一个实施例涉及一种存储器模块，其包括安装多个存储器芯片的衬底和安装到衬底上或在衬底内制造的两个或更多个稳压器。
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公开(公告)号：US20150085555A1
公开(公告)日：2015-03-26
申请号：US14394260
申请日：2012-05-01
CPC分类号： G11C8/12 , G11C5/02 , G11C5/04 , G11C29/42 , G11C2029/0411 , H01L25/0655 , H01L2924/0002 , H01L2924/00
摘要： An apparatus includes a memory module, and the memory module includes a package. The package contains memory dies, and the memory dies share a chip select line.
摘要翻译： 一种装置包括存储器模块，并且存储器模块包括封装。 该封装包含存储器管芯，并且存储器管芯共享芯片选择线。
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3.发明申请METHOD AND SYSTEM FOR POWER-EFFICIENT AND NON-SIGNAL-DEGRADING VOLTAGE REGULATION IN MEMORY SUBSYSTEMS 有权存储器件中功率有效和非信号降低电压调节的方法和系统公开(公告)号：US20120110363A1
公开(公告)日：2012-05-03
申请号：US13383359
申请日：2009-07-27
IPC分类号： G06F1/26
CPC分类号： G11C5/04 , G06F1/3225 , G11C5/147
摘要： Embodiments of the present invention are directed to a memory subsystem comprising a memory controller, multiple memory modules interconnected with the memory controller by one or more communications media, each memory module comprising a substrate to which multiple memory chips are mounted and electronically connected to the communications media, and a power-supply signal routed to two or more voltage regulators within the memory subsystem from a system power supply, the voltage regulators outputting two or more internal power signals, each power signal providing a different, regulated voltage, which are routed to each of the memory chips. Another embodiment of the present invention is directed to a memory module comprising a substrate to which multiple memory chips are mounted and two or more voltage regulators mounted to, or fabricated within, the substrate.
摘要翻译： 本发明的实施例涉及一种存储器子系统，包括存储器控制器，通过一个或多个通信介质与存储器控制器互连的多个存储器模块，每个存储器模块包括衬底，多个存储器芯片被安装到该衬底上并且电连接到通信 介质和从系统电源路由到存储器子系统内的两个或更多个稳压器的电源信号，电压调节器输出两个或更多个内部功率信号，每个功率信号提供不同的调节电压，其被路由到 每个内存芯片。 本发明的另一个实施例涉及一种存储器模块，其包括安装多个存储器芯片的衬底和安装到衬底上或在衬底内制造的两个或更多个稳压器。
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公开(公告)号：US20110115454A1
公开(公告)日：2011-05-19
申请号：US12936674
申请日：2008-04-08
IPC分类号： G05F1/46
CPC分类号： H02M3/156 , H02M2001/0019
摘要： A voltage regulator is provided that includes current sense circuitry configured to detect an amount of current provided to a load, a voltage controlled oscillator configured to output a clock signal with a constant duty cycle at a frequency that varies in dependence on the amount of current detected by current sense circuitry, and regulator circuitry configured to provide a regulated voltage to the load using the clock signal.
摘要翻译： 提供了一种电压调节器，其包括被配置为检测提供给负载的电流量的电流感测电路;压控振荡器，被配置为以一定频率输出具有恒定占空比的时钟信号，该频率根据检测到的电流量而变化 以及调节器电路，其被配置为使用时钟信号向负载提供调节电压。
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5.发明授权Electronic apparatus having I/O board with cable-free redundant adapter cards thereon 失效具有I / O板的电子设备，其上具有无电缆冗余适配器卡
公开(公告)号：US5986880A
公开(公告)日：1999-11-16
申请号：US876730
申请日：1997-06-16
CPC分类号： G06F13/409
摘要： The cage-supported hard disk drives in a computer server system are coupled to connectors on the cage back plane circuit boards and are controlled by a pair of array controller cards which are hot-plug connected in a redundant manner on the system I/O board using a pair of connectors mounted on the I/O board, each connector having first and second sets of electrical contacts thereon. Connector edge portions of the array controller cards are plugged into the I/O board connectors and have first and second sets of electrical contacts that engage the corresponding first and second sets of electrical contacts on their associated I/O board connectors. Formed on the I/O board are (1) a peripheral interconnect bus structure connected to the first sets of connector electrical contacts, (2) an electrical bus structure connected to the second sets of connector electrical contacts and associated cable connectors, and (3) an intercontroller bus structure connected between the second sets of connector electrical contacts and enabling the two array controller cards to communicate with one another independently of the peripheral interconnect bus structure. Electrical cables are interconnected between the electrical bus structure and the back plane circuit boards to couple the array controller cards thereto in a redundant control manner without requiring direct cable connection to either of the array controller cards.
摘要翻译： 计算机服务器系统中的笼式硬盘驱动器耦合到保持架背板电路板上的连接器，并由一对阵列控制器卡控制，这些阵列控制器卡以冗余方式热插拔连接到系统I / O板上 使用安装在I / O板上的一对连接器，每个连接器在其上具有第一组和第二组电触点。 阵列控制器卡的连接器边缘部分插入到I / O板连接器中，并且具有接合在其相关联的I / O板连接器上的对应的第一和第二组电触头的第一组和第二组电触点。 在I / O板上形成有（1）连接到第一组连接器电触点的外围互连总线结构，（2）连接到第二组连接器电触头和相关电缆连接器的电总线结构，和（3 ）连接在所述第二组连接器电触头之间并且使得所述两个阵列控制器卡能够独立于所述外围互连总线结构彼此通信的互连控制器总线结构。 电气电缆在电气总线结构和背板电路板之间互连，以便以冗余控制方式将阵列控制器卡耦合到其上，而不需要直接连接到阵列控制器卡中的任何一个。
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公开(公告)号：US07594128B2
公开(公告)日：2009-09-22
申请号：US11193834
申请日：2005-07-29
CPC分类号： G06F1/3228
摘要： In at least some embodiments, a system comprises a processor and a memory coupled to the processor. The memory stores processor performance utility instructions and performance adjustment instructions. When executed, the processor performance utility instructions are configured to cause activities of the processor to be counted and to cause a processor utilization value to be determined based on the counts. When executed, the performance adjustment instructions are configured to adjust the processor utilization value based on a comparison of the processor's current operating frequency and maximum operating frequency.
摘要翻译： 在至少一些实施例中，系统包括耦合到处理器的处理器和存储器。 存储器存储处理器性能实用程序指令和性能调整说明。 当执行时，处理器性能实用程序指令被配置为使得处理器的活动被计数，并且基于计数来确定处理器利用值。 当执行时，性能调整指令被配置为基于处理器的当前工作频率和最大工作频率的比较来调整处理器利用率值。
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公开(公告)号：US20100257388A1
公开(公告)日：2010-10-07
申请号：US12416523
申请日：2009-04-01
申请人： Alan M. Green , Reza M. Bacchus , Binh Nguyen
发明人： Alan M. Green , Reza M. Bacchus , Binh Nguyen
IPC分类号： G06F1/32
CPC分类号： G06F1/3225
摘要： A method for phase shedding is disclosed. The method comprises the following steps. At step one power is supplied to a memory sub-system with a multi-phase regulator wherein a maximum number of phases in the multi-phase regulator are enabled. At step two the memory configuration of the memory sub-system is determined. At step three at least one of the phases of the multi-phase regulator is disabled when the memory configuration meets a predetermined criteria.
摘要翻译： 公开了一种相位脱落的方法。 该方法包括以下步骤。 在步骤1中，使用多相调节器向存储器子系统供电，其中多相调节器中的最大相数被启用。 在步骤2中，确定存储器子系统的存储器配置。 在步骤3中，当存储器配置满足预定标准时，多相调节器的至少一个相位被禁用。
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公开(公告)号：US07222247B2
公开(公告)日：2007-05-22
申请号：US10818220
申请日：2004-04-05
申请人： Reza M. Bacchus , Kenneth T. Brown
发明人： Reza M. Bacchus , Kenneth T. Brown
摘要： A computer system determines whether a voltage signal that powers a slot circuitry and a card in one of two modes has been properly generated. If so, then the slot circuitry and the card are initialized in the one mode. Otherwise, the slot circuitry and the card are initialized in the other of the two modes.
摘要翻译： 计算机系统确定是否适当地产生了以两种模式之一对时隙电路和卡供电的电压信号。 如果是这样，则在一种模式中初始化时隙电路和卡。 否则，插槽电路和卡在两种模式中的另一种模式下被初始化。
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公开(公告)号：US07219322B2
公开(公告)日：2007-05-15
申请号：US10832633
申请日：2004-04-27
CPC分类号： H05K3/4688 , H05K1/024 , H05K3/4626
摘要： A first signal passes through a first layer of a circuit apparatus at a first propagation speed, and a second signal passes through a second layer of the circuit apparatus at a second propagation speed different from the first propagation speed.
摘要翻译： 第一信号以第一传播速度通过电路装置的第一层，第二信号以不同于第一传播速度的第二传播速度通过电路装置的第二层。
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公开(公告)号：US20140337589A1
公开(公告)日：2014-11-13
申请号：US14368769
申请日：2012-04-30
申请人： David G. Carpenter , William C. Hallowell , Craig M. Belusar , Jason W. Kinsey , Raghavan V. Venugopal , Reza M. Bacchus
发明人： David G. Carpenter , William C. Hallowell , Craig M. Belusar , Jason W. Kinsey , Raghavan V. Venugopal , Reza M. Bacchus
IPC分类号： G06F3/06
CPC分类号： G06F3/0604 , G06F3/0632 , G06F3/065 , G06F3/0685 , G06F11/1441 , G06F12/0246 , G06F13/1694 , G06F2003/0697 , G06F2212/217
摘要： A system includes a hybrid memory module. The hybrid memory module includes volatile memory and non-volatile memory. The system further includes a processor coupled to the hybrid memory module. The processor prevents the hybrid memory module from being mapped during a memory initialization routine by misrepresenting a status of the hybrid memory module.
摘要翻译： 系统包括混合存储器模块。 混合存储器模块包括易失性存储器和非易失性存储器。 该系统还包括耦合到混合存储器模块的处理器。 处理器通过错误地表示混合存储器模块的状态来防止在存储器初始化例程期间映射混合存储器模块。
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