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1.发明申请METHOD AND SYSTEM FOR POWER-EFFICIENT AND NON-SIGNAL-DEGRADING VOLTAGE REGULATION IN MEMORY SUBSYSTEMS 有权存储器件中功率有效和非信号降低电压调节的方法和系统公开(公告)号：US20120110363A1
公开(公告)日：2012-05-03
申请号：US13383359
申请日：2009-07-27
IPC分类号： G06F1/26
CPC分类号： G11C5/04 , G06F1/3225 , G11C5/147
摘要： Embodiments of the present invention are directed to a memory subsystem comprising a memory controller, multiple memory modules interconnected with the memory controller by one or more communications media, each memory module comprising a substrate to which multiple memory chips are mounted and electronically connected to the communications media, and a power-supply signal routed to two or more voltage regulators within the memory subsystem from a system power supply, the voltage regulators outputting two or more internal power signals, each power signal providing a different, regulated voltage, which are routed to each of the memory chips. Another embodiment of the present invention is directed to a memory module comprising a substrate to which multiple memory chips are mounted and two or more voltage regulators mounted to, or fabricated within, the substrate.
摘要翻译： 本发明的实施例涉及一种存储器子系统，包括存储器控制器，通过一个或多个通信介质与存储器控制器互连的多个存储器模块，每个存储器模块包括衬底，多个存储器芯片被安装到该衬底上并且电连接到通信 介质和从系统电源路由到存储器子系统内的两个或更多个稳压器的电源信号，电压调节器输出两个或更多个内部功率信号，每个功率信号提供不同的调节电压，其被路由到 每个内存芯片。 本发明的另一个实施例涉及一种存储器模块，其包括安装多个存储器芯片的衬底和安装到衬底上或在衬底内制造的两个或更多个稳压器。
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2.发明授权Method and system for power-efficient and non-signal-degrading voltage regulation in memory subsystems 有权存储器子系统中功率效率和非信号降解电压调节的方法和系统公开(公告)号：US08782452B2
公开(公告)日：2014-07-15
申请号：US13383359
申请日：2009-07-27
CPC分类号： G11C5/04 , G06F1/3225 , G11C5/147
摘要： Embodiments of the present invention are directed to a memory subsystem comprising a memory controller, multiple memory modules interconnected with the memory controller by one or more communications media, each memory module comprising a substrate to which multiple memory chips are mounted and electronically connected to the communications media, and a power-supply signal routed to two or more voltage regulators within the memory subsystem from a system power supply, the voltage regulators outputting two or more internal power signals, each power signal providing a different, regulated voltage, which are routed to each of the memory chips. Another embodiment of the present invention is directed to a memory module comprising a substrate to which multiple memory chips are mounted and two or more voltage regulators mounted to, or fabricated within, the substrate.
摘要翻译： 本发明的实施例涉及一种存储器子系统，包括存储器控制器，通过一个或多个通信介质与存储器控制器互连的多个存储器模块，每个存储器模块包括衬底，多个存储器芯片被安装到该衬底上并且电连接到通信 介质和从系统电源路由到存储器子系统内的两个或更多个稳压器的电源信号，电压调节器输出两个或更多个内部功率信号，每个功率信号提供不同的调节电压，其被路由到 每个内存芯片。 本发明的另一个实施例涉及一种存储器模块，其包括安装多个存储器芯片的衬底和安装到衬底上或在衬底内制造的两个或更多个稳压器。
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公开(公告)号：US20110115454A1
公开(公告)日：2011-05-19
申请号：US12936674
申请日：2008-04-08
IPC分类号： G05F1/46
CPC分类号： H02M3/156 , H02M2001/0019
摘要： A voltage regulator is provided that includes current sense circuitry configured to detect an amount of current provided to a load, a voltage controlled oscillator configured to output a clock signal with a constant duty cycle at a frequency that varies in dependence on the amount of current detected by current sense circuitry, and regulator circuitry configured to provide a regulated voltage to the load using the clock signal.
摘要翻译： 提供了一种电压调节器，其包括被配置为检测提供给负载的电流量的电流感测电路;压控振荡器，被配置为以一定频率输出具有恒定占空比的时钟信号，该频率根据检测到的电流量而变化 以及调节器电路，其被配置为使用时钟信号向负载提供调节电压。
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公开(公告)号：US07783822B2
公开(公告)日：2010-08-24
申请号：US11828042
申请日：2007-07-25
IPC分类号： G06F13/00
CPC分类号： H04L45/00 , H04L45/122
摘要： Systems and methods for improving performance of a rentable fabric are disclosed. In an exemplary embodiment a system may comprise a plurality of compute nodes, a routable fabric, and a plurality of chipsets connected by the routable fabric to the plurality of compute nodes. The chipsets have range registers dynamically directing traffic from any device to any of the plurality of compute nodes over the routable fabric.
摘要翻译： 公开了用于提高可出租织物性能的系统和方法。 在示例性实施例中，系统可以包括多个计算节点，可路由结构以及由可路由结构连接到多个计算节点的多个芯片组。 芯片组具有动态地将流量从任何设备引导到可路由结构上的多个计算节点中的任何一个的范围寄存器。
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公开(公告)号：US20150095564A1
公开(公告)日：2015-04-02
申请号：US14396600
申请日：2012-05-09
IPC分类号： G11C7/10 , G11C11/406
CPC分类号： G11C7/1072 , G11C8/12 , G11C11/40615 , G11C11/4087 , G11C29/846
摘要： An apparatus includes a memory module, which includes a memory array. The memory array includes rows of memory and columns of memory. The apparatus also includes at least one row of memory not in the memory array and a register. The register includes an address space and a row/column indicator. The apparatus also includes row selection logic to select the at least one row to be activated if the address from an address bus equals the register value and if the row/column indicator indicates row.
摘要翻译： 一种装置包括存储器模块，其包括存储器阵列。 存储器阵列包括存储器行和存储器列。 该装置还包括不在存储器阵列中的至少一行存储器和寄存器。 该寄存器包括地址空间和行/列指示符。 如果来自地址总线的地址等于寄存器值，并且行/列指示符指示行，则该设备还包括行选择逻辑以选择要激活的至少一行。
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公开(公告)号：US20140372682A1
公开(公告)日：2014-12-18
申请号：US14368573
申请日：2012-03-27
申请人： Melvin K. Benedict
发明人： Melvin K. Benedict
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7201 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/22 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2013/0088 , G11C2207/2272
摘要： A nonvolatile memory (10) is partitioned into bank groups (24) based upon a write-to-read latency of the nonvolatile memory (10).
摘要翻译： 基于非易失性存储器（10）的写入 - 读取等待时间，非易失性存储器（10）被划分为存储体组（24）。
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公开(公告)号：US20130326293A1
公开(公告)日：2013-12-05
申请号：US13485824
申请日：2012-05-31
CPC分类号： G11C29/44 , G06F11/2205 , G06F11/27 , G11C5/04 , G11C29/028 , G11C29/08 , G11C29/56008 , G11C29/76 , G11C2029/0401 , G11C2029/0409
摘要： An error test routine is to test for a type of memory error by changing a content of a memory module. A memory handling procedure is to isolate the memory error in response to a positive outcome of the error test routine. The error test routine and memory handling procedure is to be performed at runtime transparent to an operating system. Information corresponding to isolating the memory error is stored.
摘要翻译： 错误测试例程是通过更改内存模块的内容来测试一种内存错误。 存储器处理过程是响应于错误测试例程的肯定结果来隔离存储器错误。 错误测试程序和内存处理程序将在运行时对操作系统透明执行。 存储与隔离存储器错误相对应的信息。
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公开(公告)号：US20090080164A1
公开(公告)日：2009-03-26
申请号：US11859601
申请日：2007-09-21
IPC分类号： H05K1/14
CPC分类号： H05K1/148 , H05K1/141 , H05K2201/045 , H05K2201/10159
摘要： A system in some embodiments includes a system having a memory module having a first board comprising a first plurality of memory receptacles configured to support a first plurality of in-line memory modules in an overlapping relationship with a second plurality of in-line memory modules disposed on a second board. Further, a method in some embodiments includes rotating first and second memory boards into a parallel configuration via a hinge coupling the first and second memory boards, and inserting the first and second memory boards into first and second board connectors simultaneously.
摘要翻译： 在一些实施例中的系统包括具有存储器模块的系统，该存储器模块具有第一板，所述第一板包括第一多个存储器插槽，其被配置为以与第二多个在线存储器模块布置的重叠关系支持第一组多个在线存储器模块 在第二板上。 此外，在一些实施例中的方法包括经由联接第一和第二存储器板的铰链将第一和第二存储器板旋转成并联配置，以及将第一和第二存储器板同时插入第一和第二板连接器。
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公开(公告)号：US20150143186A1
公开(公告)日：2015-05-21
申请号：US14395951
申请日：2012-07-27
申请人： Melvin K. Benedict
发明人： Melvin K. Benedict
IPC分类号： G11C29/08
CPC分类号： G11C29/08 , G11C5/04 , G11C29/022 , G11C29/10
摘要： DIMM seating errors may be detected. An example detection method includes determining whether a training error has occurred for a number of dynamic random access memories (DRAMs) of a DIMM. The Example method includes identifying a location for each of the DRAMs. The example method includes determining whether a seating error has occurred based on the training error, the number, and the location of the DRAMs.
摘要翻译： 可能会检测到DIMM座位错误。 一种示例性检测方法包括确定对于DIMM的多个动态随机存取存储器（DRAM）是否已经发生训练误差。 该示例方法包括识别每个DRAM的位置。 该示例方法包括基于训练误差，数量和DRAM的位置确定是否发生了座位错误。
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公开(公告)号：US20090031070A1
公开(公告)日：2009-01-29
申请号：US11828042
申请日：2007-07-25
IPC分类号： G06F13/00
CPC分类号： H04L45/00 , H04L45/122
摘要： Systems and methods for improving performance of a rentable fabric are disclosed. In an exemplary embodiment a system may comprise a plurality of compute nodes, a routable fabric, and a plurality of chipsets connected by the routable fabric to the plurality of compute nodes. The chipsets have range registers dynamically directing traffic from any device to any of the plurality of compute nodes over the routable fabric.
摘要翻译： 公开了用于提高可出租织物性能的系统和方法。 在示例性实施例中，系统可以包括多个计算节点，可路由结构以及由可路由结构连接到多个计算节点的多个芯片组。 芯片组具有动态地将流量从任何设备引导到可路由结构上的多个计算节点中的任何一个的范围寄存器。
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