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公开(公告)号：US5448193A
公开(公告)日：1995-09-05
申请号：US290170
申请日：1994-08-15
摘要： An integrated circuit includes a clock alignment circuit having a frequency synthesizer for receiving a reference clock signal at a lower frequency and for generating phases of an oscillator clock signal at a higher frequency. The oscillator clock signal phases drive a desired clock signal generating circuit that generates various phases of the desired clock signal. The desired clock signal phases are systematically compared to the reference clock signal. The phase of the desired clock signal that is determined to align with the reference clock signal is provided as the desired clock signal output from the integrated circuit such that there is no apparent time delay through the integrated circuit. In an alternate embodiment, a single phase of the desired clock signal is selected and a phase locked loop adjusts the oscillator in the frequency synthesizer to align the selected phase of the desired clock signal with the reference clock signal.
摘要翻译： 集成电路包括具有频率合成器的时钟对准电路，频率合成器用于接收较低频率的参考时钟信号，并产生较高频率的振荡器时钟信号的相位。 振荡器时钟信号相位驱动期望的时钟信号产生电路，其产生所需时钟信号的各个相位。 所需的时钟信号相位与参考时钟信号进行系统比较。 被确定为与参考时钟信号对准的期望时钟信号的相位被提供为从集成电路输出的期望时钟信号，使得通过集成电路没有明显的时间延迟。 在替代实施例中，选择期望时钟信号的单相，并且锁相环调节频率合成器中的振荡器，以将期望时钟信号的所选相位与参考时钟信号对准。
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公开(公告)号：US5268656A
公开(公告)日：1993-12-07
申请号：US971785
申请日：1992-11-05
申请人： Richard Muscavage
发明人： Richard Muscavage
IPC分类号： G06F1/08 , G06F1/10 , G06F15/78 , H03B27/00 , H03K5/00 , H03K5/13 , H03K5/15 , H03L7/081 , H03L7/099
CPC分类号： H03B27/00 , H03L7/081 , H03L7/0996 , H03K2005/00234 , H03K2005/00241
摘要： An integrated circuit has an oscillator for generating a plurality of phases of an oscillator clock signal. Each phase of the oscillator clock clocks a respective one of a plurality of ring shift registers. The output of each stage of the ring shift registers is a phase of a desired clock signal and is an input to a multiplexer that can selectively provide one of the desired clock phases as the output of the multiplexer. In another embodiment of the invention the ring shift registers generate half of the phases of a desired clock signal at a multiple of the desired frequency. The multiplexer output clocks a divide by two circuit which is followed by another level of multiplexing to generate the other half of the phases and to divide down to the desired frequency.
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公开(公告)号：US20110002186A1
公开(公告)日：2011-01-06
申请号：US12496624
申请日：2009-07-01
IPC分类号： G11C17/18
CPC分类号： G11C17/18
摘要： An electrically programmable fuse, a method of operating the same and an integrated circuit (IC) incorporating the fuse or the method. In one embodiment, the fuse includes: (1) at least one fuse element configured to be programmed with contents and (2) an inhibitor coupled to the at least one fuse element and configured to be activated to inhibit subsequent reprogramming of the at least one fuse element.
摘要翻译： 一种电可编程保险丝，一种操作该保险丝的方法，以及一种结合该保险丝或该方法的集成电路（IC）。 在一个实施例中，熔丝包括：（1）至少一个熔丝元件，其被配置为对内容物进行编程;以及（2）抑制器，其耦合到所述至少一个熔丝元件并被配置为被激活以禁止所述至少一个熔丝元件的后续重新编程 保险丝元件
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4.发明申请Integrated Circuit Performance Enhancement Using On-Chip Adaptive Voltage Scaling 失效使用片上自适应电压调节的集成电路性能增强公开(公告)号：US20100115475A1
公开(公告)日：2010-05-06
申请号：US12261738
申请日：2008-10-30
申请人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
发明人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F2217/78
摘要： Techniques for enhancing the performance of an IC are provided. A method of enhancing IC performance includes the steps of: associating at least one performance result of at least one performance monitor, formed on the IC, with deterministic combinations of IC performance and a processing parameter, a supply voltage, and/or a temperature of the IC; determining an IC processing characterization of the IC as a function of the performance result for at least one prescribed supply voltage and temperature of the IC, the IC processing characterization being indicative of a type of processing received by the IC during fabrication of the IC; and controlling a voltage supplied to at least a portion of the IC, the voltage being controlled as a function of the IC processing characterization and/or the temperature of the IC so as to satisfy at least one prescribed performance parameter of the IC.
摘要翻译： 提供了用于提高IC性能的技术。 一种提高IC性能的方法包括以下步骤：将形成在IC上的至少一个性能监视器的至少一个性能结果与IC性能与处理参数，电源电压和/或 IC; 根据IC的至少一个规定电源电压和温度的性能结果确定IC的IC处理特征，IC处理特性表示IC在制造IC期间接收的处理类型; 以及控制提供给所述IC的至少一部分的电压，所述电压作为所述IC处理特征和/或所述IC的温度的函数被控制，以满足所述IC的至少一个规定的性能参数。
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5.发明申请PCB INCLUDING MULTIPLE CHIPS SHARING AN OFF-CHIP MEMORY, A METHOD OF ACCESSING OFF-CHIP MEMORY AND A MCM UTILIZING FEWER OFF-CHIP MEMORIES THAN CHIPS 审中-公开PCB包括多个CHIPS共享一个片外存储器，一种使用片外存储器的方法和一个使用更快的片外存储器的MCM公开(公告)号：US20100017569A1
公开(公告)日：2010-01-21
申请号：US12174566
申请日：2008-07-16
IPC分类号： G06F12/00
CPC分类号： G06F12/0284
摘要： A PCB having fewer off-chip memories than chips, a MCM, and a method of accessing an off-chip shared memory space. In one embodiment, the method includes: (1) generating a memory request at a first chip of the printed circuit board, (2) transforming the memory request to a shared memory request and (3) directing the shared memory request to an off-chip shared memory space indirectly coupled to the first chip via a second chip of the printed circuit board.
摘要翻译： 具有比芯片更少的片外存储器的PCB，MCM以及访问片外共享存储器空间的方法。 在一个实施例中，该方法包括：（1）在印刷电路板的第一芯片处产生存储器请求，（2）将存储器请求转换为共享存储器请求，以及（3）将共享存储器请求引导到关闭状态， 通过印刷电路板的第二芯片间接地耦合到第一芯片的芯片共享存储器空间。
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6.发明授权Computer peripheral device having the capability to wake up from a cold state with information stored before cold powerdown 有权计算机外围设备具有从冷启动状态存储的信息从冷态唤醒的能力公开(公告)号：US06282666B1
公开(公告)日：2001-08-28
申请号：US09257954
申请日：1999-02-26
IPC分类号： G06F1202
CPC分类号： G06F1/3253 , G06F1/3203 , Y02D10/151
摘要： A computer peripheral device suitable for operation with a Peripheral Component Interconnect (PCI) Bus or the like, has the ability to “wakeup” the bus from a cold state (e.g., D3cold) without the need to supply auxiliary power (e.g., 3.3 volts) to the entire device during the cold state. A modem in the preferred embodiment (although the invention is applicable to other peripheral devices), the device latches device status information from the main circuitry of the device (operating on 5 volts, for example) into a “keep alive” circuit connected to the auxiliary power supply upon the falling edge of a PCI reset signal (RST#). Additionally, the auxiliary power supply also powers a ring detect circuit for the detection of an incoming telephone call, which incoming call triggers a Power Management Event (PME#) signal for changing the state of the bus to an active state. Further, the auxiliary power supply powers a RST# detection circuit for indicating that a change in the power state of the bus is imminent.
摘要翻译： 适用于使用外围组件互连（PCI）总线等的计算机外围设备具有从总线“冷却”（例如，D3cold）唤醒总线的能力，而不需要提供辅助电源（例如，3.3伏特 ）在冷态期间到整个设备。 在优选实施例中的调制解调器（尽管本发明可应用于其他外围设备），设备将来自设备的主电路（例如，在5伏特上工作）的设备状态信息锁定到连接到 辅助电源在PCI复位信号（RST＃）的下降沿。 此外，辅助电源还为环路检测电路供电以检测进入的电话呼叫，该来电呼叫触发电力管理事件（PME＃）信号，以将总线的状态改变为活动状态。 此外，辅助电源为RST＃检测电路供电，用于指示总线的功率状态的改变即将到来。
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公开(公告)号：US09158359B2
公开(公告)日：2015-10-13
申请号：US13428862
申请日：2012-03-23
申请人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
发明人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
CPC分类号： G06F1/3209 , G06F1/325 , G06F1/3296 , Y02D10/172 , Y10T307/406
摘要： An adaptive voltage scaling system includes first and second devices. Each of the first and second devices includes at least one master serial interface port and at least one slave serial interface port. The first device is operatively coupled to a voltage regulator, and the slave serial interface port associated with the second device is operatively coupled to the master serial interface port associated with the first device. The first device controls the voltage regulator based on information obtained from the first and second devices using the master serial interface port associated with the first device and the slave serial interface port associated with the second device. The first and second devices receive voltage from the voltage regulator. A corresponding method and computer-readable medium are also disclosed.
摘要翻译： 自适应电压缩放系统包括第一和第二装置。 第一和第二设备中的每一个包括至少一个主串行接口端口和至少一个从串行接口端口。 第一设备可操作地耦合到电压调节器，并且与第二设备相关联的从串行接口端口可操作地耦合到与第一设备相关联的主串行接口端口。 第一设备使用与第一设备相关联的主串行接口端口和与第二设备相关联的从串行接口端口，基于从第一和第二设备获得的信息来控制电压调节器。 第一和第二器件从电压调节器接收电压。 还公开了相应的方法和计算机可读介质。
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公开(公告)号：US20130249290A1
公开(公告)日：2013-09-26
申请号：US13428862
申请日：2012-03-23
申请人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
发明人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
IPC分类号： H02J1/00
CPC分类号： G06F1/3209 , G06F1/325 , G06F1/3296 , Y02D10/172 , Y10T307/406
摘要： An adaptive voltage scaling system includes first and second devices. Each of the first and second devices includes at least one master serial interface port and at least one slave serial interface port. The first device is operatively coupled to a voltage regulator, and the slave serial interface port associated with the second device is operatively coupled to the master serial interface port associated with the first device. The first device controls the voltage regulator based on information obtained from the first and second devices using the master serial interface port associated with the first device and the slave serial interface port associated with the second device. The first and second devices receive voltage from the voltage regulator. A corresponding method and computer-readable medium are also disclosed.
摘要翻译： 自适应电压缩放系统包括第一和第二装置。 第一和第二设备中的每一个包括至少一个主串行接口端口和至少一个从串行接口端口。 第一设备可操作地耦合到电压调节器，并且与第二设备相关联的从串行接口端口可操作地耦合到与第一设备相关联的主串行接口端口。 第一设备使用与第一设备相关联的主串行接口端口和与第二设备相关联的从串行接口端口，基于从第一和第二设备获得的信息来控制电压调节器。 第一和第二器件从电压调节器接收电压。 还公开了相应的方法和计算机可读介质。
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公开(公告)号：US08350589B2
公开(公告)日：2013-01-08
申请号：US12738931
申请日：2009-01-27
CPC分类号： H03K19/00 , G01R31/31858 , H03K5/135
摘要： An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.
摘要翻译： 公开了一种具有用于监视具有目标定时裕度的关键路径中的定时的监视器电路的集成电路。 监视器电路具有两个移位寄存器，其中之一包括向接收信号施加延迟值的延迟元件。 两个移位寄存器的输入形成能够接收输入信号的信号输入节点。 监视器电路还具有一个具有输出和至少两个输入的逻辑门，每个输入连接到两个移位寄存器的相应输出之一。 逻辑门的输出指示目标定时裕度是否满足或不满足。
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10.发明授权Integrated circuit performance enhancement using on-chip adaptive voltage scaling 失效使用片上自适应电压调整的集成电路性能提升公开(公告)号：US08161431B2
公开(公告)日：2012-04-17
申请号：US12261738
申请日：2008-10-30
申请人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
发明人： Michael S. Buonpane , James D. Chlipala , Richard P. Martin , Richard Muscavage , Scott A. Segan
CPC分类号： G06F17/5063 , G06F2217/78
摘要： Techniques for enhancing the performance of an IC are provided. A method of enhancing IC performance includes the steps of: associating at least one performance result of at least one performance monitor, formed on the IC, with deterministic combinations of IC performance and a processing parameter, a supply voltage, and/or a temperature of the IC; determining an IC processing characterization of the IC as a function of the performance result for at least one prescribed supply voltage and temperature of the IC, the IC processing characterization being indicative of a type of processing received by the IC during fabrication of the IC; and controlling a voltage supplied to at least a portion of the IC, the voltage being controlled as a function of the IC processing characterization and/or the temperature of the IC so as to satisfy at least one prescribed performance parameter of the IC.
摘要翻译： 提供了用于提高IC性能的技术。 一种提高IC性能的方法包括以下步骤：将形成在IC上的至少一个性能监视器的至少一个性能结果与IC性能与处理参数，电源电压和/或 IC; 根据IC的至少一个规定电源电压和温度的性能结果确定IC的IC处理特征，IC处理特性表示IC在制造IC期间接收的处理类型; 以及控制提供给所述IC的至少一部分的电压，所述电压作为所述IC处理特征和/或所述IC的温度的函数被控制，以满足所述IC的至少一个规定的性能参数。
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