公开(公告)号：US5486783A

公开(公告)日：1996-01-23

申请号：US332202

申请日：1994-10-31

申请人： Robert J. Baumert ,  Robert L. Pritchett

发明人： Robert J. Baumert ,  Robert L. Pritchett

IPC分类号： G06F1/10 ,  H03L7/081 ,  H03L7/06

CPC分类号： H03L7/0812 ,  G06F1/10

摘要： The present invention relates to a circuit board having a plurality of integrated circuits provided thereon, wherein each integrated circuit (IC) receives a common clocked input reference signal and outputs a dam signal. Each integrated circuit is provided with a de-skewing circuit which compensates for signal delays in the IC so as to synchronize the output data signal with the clocked input reference signal. The de-skewing circuit is operative to generate a simulated signal delay to the input signal which emulates the signal delays of the IC.

摘要翻译： 本发明涉及一种具有设置在其上的多个集成电路的电路板，其中每个集成电路（IC）接收公共时钟输入参考信号并输出​​大坝信号。 每个集成电路设置有去偏移电路，其补偿IC中的信号延迟，以使输出数据信号与时钟输入参考信号同步。 去偏斜电路可操作以产生模拟IC的信号延迟的输入信号的模拟信号延迟。

公开(公告)号：US5448193A

公开(公告)日：1995-09-05

申请号：US290170

申请日：1994-08-15

申请人： Robert J. Baumert ,  Richard Muscavage ,  Robert L. Pritchett

发明人： Robert J. Baumert ,  Richard Muscavage ,  Robert L. Pritchett

IPC分类号： H03K5/13 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  H03K5/15 ,  H03L7/00 ,  H03L7/183

CPC分类号： G06F1/08 ,  G06F1/10

摘要： An integrated circuit includes a clock alignment circuit having a frequency synthesizer for receiving a reference clock signal at a lower frequency and for generating phases of an oscillator clock signal at a higher frequency. The oscillator clock signal phases drive a desired clock signal generating circuit that generates various phases of the desired clock signal. The desired clock signal phases are systematically compared to the reference clock signal. The phase of the desired clock signal that is determined to align with the reference clock signal is provided as the desired clock signal output from the integrated circuit such that there is no apparent time delay through the integrated circuit. In an alternate embodiment, a single phase of the desired clock signal is selected and a phase locked loop adjusts the oscillator in the frequency synthesizer to align the selected phase of the desired clock signal with the reference clock signal.

摘要翻译： 集成电路包括具有频率合成器的时钟对准电路，频率合成器用于接收较低频率的参考时钟信号，并产生较高频率的振荡器时钟信号的相位。 振荡器时钟信号相位驱动期望的时钟信号产生电路，其产生所需时钟信号的各个相位。 所需的时钟信号相位与参考时钟信号进行系统比较。 被确定为与参考时钟信号对准的期望时钟信号的相位被提供为从集成电路输出的期望时钟信号，使得通过集成电路没有明显的时间延迟。 在替代实施例中，选择期望时钟信号的单相，并且锁相环调节频率合成器中的振荡器，以将期望时钟信号的所选相位与参考时钟信号对准。

公开(公告)号：US5337022A

公开(公告)日：1994-08-09

申请号：US982817

申请日：1992-11-30

申请人： Robert L. Pritchett

发明人： Robert L. Pritchett

IPC分类号： H03L7/095 ,  H03L7/18 ,  H03L7/00

CPC分类号： H03L7/095 ,  H03L2207/14 ,  Y10S331/02

摘要： An integrated circuit for detecting harmonic lock of a phase-locked loop includes a frequency synthesizer for receiving a reference clock signal and for generating an oscillator clock signal. A phase generator receives the oscillator clock signal and generates a phase of the oscillator clock signal. A shift register receives as an input the reference clock signal and is clocked by the phase of the oscillator clock signal to produce an output that is a repetitive sequence of logic states. In an alternate embodiment, a harmonic decode circuit decodes the shift register output to determine which harmonic the phase-locked loop has locked onto.

摘要翻译： 用于检测锁相环的谐波锁定的集成电路包括用于接收参考时钟信号并用于产生振荡器时钟信号的频率合成器。 相位发生器接收振荡器时钟信号并产生振荡器时钟信号的相位。 移位寄存器接收参考时钟信号作为输入，并由振荡器时钟信号的相位计时，以产生作为逻辑状态的重复序列的输出。 在替代实施例中，谐波解码电路对移位寄存器输出进行解码以确定锁相环锁定的谐波。

公开(公告)号：US4789825A

公开(公告)日：1988-12-06

申请号：US161304

申请日：1988-02-25

申请人： John A. Carelli ,  Richard A. Pedersen ,  Robert L. Pritchett

发明人： John A. Carelli ,  Richard A. Pedersen ,  Robert L. Pritchett

IPC分类号： G01R31/26

CPC分类号： G01R31/2621

摘要： An integrated circuit includes first and second field effect transistors having differing channel lengths, and a means for comparing the channel currents flowing therethrough. An excessive difference of currents indicates "short channel" effects, which can degrade performance. A signal flag indicating this condition may be provided to a test pad on the chip, or used to disable operation of the integrated circuit, or otherwise used to provide an indication.

摘要翻译： 集成电路包括具有不同沟道长度的第一和第二场效应晶体管，以及用于比较流过其中的沟道电流的装置。 电流过大表示“短通道”效应，会降低性能。 指示该条件的信号标志可以提供给芯片上的测试焊盘，或用于禁止集成电路的操作，或用于提供指示。

公开(公告)号：US5302916A

公开(公告)日：1994-04-12

申请号：US992882

申请日：1992-12-21

申请人： Robert L. Pritchett

发明人： Robert L. Pritchett

IPC分类号： H03L7/087 ,  H03L7/089 ,  H03L7/00

CPC分类号： H03L7/089

摘要： An integrated circuit for generating an oscillator clock signal based on a reference clock signal includes a wide band digital frequency detector. The wide band digital frequency detector includes a first shift register clocked by the reference clock signal and a second shift register clocked by the oscillator clock signal. A third shift register receives as an input the output from the first shift register and is clocked by the output of the second shift register. The third shift register provides a first oscillator control output. A fourth shift register receives a phase of the reference clock signal as an input and is clocked by the oscillator clock signal to provide a second oscillator control output. In an alternate embodiment, the first oscillator control output is coupled as the up-down control input of an up-down counter and the second oscillator control output is coupled as the clock input to the up-down counter to control the oscillator clock frequency.

摘要翻译： 用于基于参考时钟信号产生振荡器时钟信号的集成电路包括宽带数字频率检测器。 宽带数字频率检测器包括由参考时钟信号计时的第一移位寄存器和由振荡器时钟信号计时的第二移位寄存器。 第三移位寄存器接收来自第一移位寄存器的输出作为输入，并由第二移位寄存器的输出计时。 第三个移位寄存器提供第一个振荡器控制输出。 第四移位寄存器接收参考时钟信号的相位作为输入，并由振荡器时钟信号计时，以提供第二振荡器控制输出。 在替代实施例中，第一振荡器控制输出作为升降计数器的上拉控制输入耦合，并且第二振荡器控制输出作为时钟输入耦合到升降计数器以控制振荡器时钟频率。

公开(公告)号：US4947061A

公开(公告)日：1990-08-07

申请号：US310407

申请日：1989-02-13

申请人： Peter C. Metz ,  Robert L. Pritchett

发明人： Peter C. Metz ,  Robert L. Pritchett

IPC分类号： H03K19/0185

CPC分类号： H03K19/018521

摘要： Disclosed is an output buffer circuit which converts from CMOS to ECL voltage levels using only CMOS technology. An external resistor provides the buffer with reference voltage levels in combination with a reference circuit. The high and low voltage references are coupled to the gates of separate biasing transistors in separate branches of the buffer circuit. A third transistor controls whether one or both branches will be coupled to the buffer output. In the first case, the low voltage level is established, and in the second case, the high voltage level is set. Additional transistors can be provided to remove charge buildup on the third transistor.

摘要翻译： 公开了一种输出缓冲器电路，其仅使用CMOS技术将CMOS转换为ECL电压电平。 外部电阻为参考电压提供了参考电压电平的缓冲器。 高和低电压基准耦合到缓冲电路的单独分支中的分离的偏置晶体管的栅极。 第三晶体管控制一个或两个分支是否耦合到缓冲器输出。 在第一种情况下，建立低电压电平，在第二种情况下，设置高电压电平。 可以提供额外的晶体管以去除第三晶体管上的电荷积累。

公开(公告)号：US07075796B1

公开(公告)日：2006-07-11

申请号：US11111623

申请日：2005-04-21

申请人： Robert L. Pritchett

发明人： Robert L. Pritchett

IPC分类号： H05K5/02 ,  H05K7/20

CPC分类号： G06F1/186 ,  G06F1/184 ,  G06F1/185 ,  H05K7/1408 ,  H05K7/1424 ,  H05K7/1431

摘要： Embodiments include apparatus, methods, and systems providing a cage for printed circuit boards. One exemplary embodiment provides a cage for housing plural printed circuit boards. The cage includes first and second side walls oppositely disposed and connected to a printed circuit board (PCB). Each side wall has plural guide mechanisms for receiving and guiding edges of plural PCBs into the cage. The cage further includes a front wall having a guide mechanism for receiving and slidingly engaging with the first and second side walls. The first, second, and front walls form an enclosure for housing the plural PCBs in a stacked configuration.

摘要翻译： 实施例包括为印刷电路板提供保持架的装置，方法和系统。 一个示例性实施例提供了一种用于容纳多个印刷电路板的保持架。 保持架包括相对设置并连接到印刷电路板（PCB）的第一和第二侧壁。 每个侧壁具有用于接收和引导多个PCB的边缘进入保持架的多个引导机构。 保持架还包括具有用于接收并滑动地与第一和第二侧壁接合的引导机构的前壁。 第一，第二和前壁形成用于以堆叠构造容纳多个PCB的外壳。

公开(公告)号：US4130827A

公开(公告)日：1978-12-19

申请号：US747366

申请日：1976-12-03

申请人： Frederick A. D'Altroy ,  Adrian R. Hartman ,  Richard M. Jacobs ,  Robert L. Pritchett ,  Peter W. Shackle

发明人： Frederick A. D'Altroy ,  Adrian R. Hartman ,  Richard M. Jacobs ,  Robert L. Pritchett ,  Peter W. Shackle

IPC分类号： H01L27/06 ,  H01L21/761 ,  H01L21/822 ,  H01L27/102 ,  H01L29/167 ,  H01L29/74 ,  H02M1/08 ,  H03K17/735

CPC分类号： H01L27/1027 ,  H01L29/167 ,  H03K17/735

摘要： A semiconductor junction-isolated PNPN crosspoint switch array has a plurality of crosspoint switches that are each formed of four regions of alternating conductivity type in a semiconductor substrate. Low enough leakage to allow the crosspoint switch array to be used in large telephone switching systems is achieved by proper selection of the thickness of the semiconductor regions and by appropriate gold doping thereof.

摘要翻译： 半导体结隔离PNPN交叉点开关阵列具有多个交叉点开关，每个交叉点开关由半导体衬底中的交替导电类型的四个区域形成。 通过适当选择半导体区域的厚度和适当的金掺杂来实现足够低的泄漏以允许交叉点开关阵列用于大型电话交换系统。