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    Kicker for non-volatile memory drain bias
    1.
    发明授权
    Kicker for non-volatile memory drain bias 有权
    Kicker用于非易失性存储器漏极偏置

    公开(公告)号：US06744671B2

    公开(公告)日：2004-06-01

    申请号：US09752550

    申请日：2000-12-29

    申请人： Ritesh Trivedi ,  Robert Baltar ,  Mark Bauer ,  Sandeep Guliani ,  Balajl Srinivasan

    发明人： Ritesh Trivedi ,  Robert Baltar ,  Mark Bauer ,  Sandeep Guliani ,  Balajl Srinivasan

    IPC分类号： G11C1606

    CPC分类号： G11C16/24 ,  G11C16/28

    摘要： An apparatus and method are disclosed for providing a kicker function for non-volatile memory drain bias. According to one embodiment, the kicker function is provided by a high performance transistor that is activated by a kicker enable signal, providing a kicker function for non-volatile memory drain bias. According to one embodiment, the kicker function is provided by a high performance transistor that is activated by a kicker enable signal.

    摘要翻译： 公开了一种用于为非易失性存储器漏极偏置提供踢球功能的装置和方法。 根据一个实施例，通过由猝发器使能信号激活的高性能晶体管提供踢icker功能，为非易失性存储器漏极偏置提供踢击功能。 根据一个实施例，通过由启动器使能信号激活的高性能晶体管来提供启动器功能。

    Method and apparatus for sen-ref equalization
    5.
    发明授权
    Method and apparatus for sen-ref equalization 有权
    传感器均衡的方法和装置

    公开(公告)号：US06717856B2

    公开(公告)日：2004-04-06

    申请号：US09896446

    申请日：2001-06-30

    申请人： Balaji Srinivasan ,  Sandeep Guliani

    发明人： Balaji Srinivasan ,  Sandeep Guliani

    IPC分类号： G11C1606

    CPC分类号： G11C16/28

    摘要： In one embodiment, the invention is an apparatus. The apparatus includes a first drain bias network having an input suitable to couple to a FLASH cell. The apparatus also includes a second drain bias network having an input suitable to couple to a FLASH cell. The apparatus further includes an equalization circuit having a first node coupled to the input of the first drain bias network and having a second node coupled to the input of the second drain bias network and having a control signal to control operation of the equalization circuit.

    摘要翻译： 在一个实施例中，本发明是一种装置。 该装置包括具有适于耦合到闪存单元的输入的第一漏极偏置网络。 该装置还包括具有适于耦合到闪存单元的输入的第二漏极偏置网络。 该装置还包括均衡电路，其具有耦合到第一漏极偏置网络的输入的第一节点，并且具有耦合到第二漏极偏置网络的输入的第二节点并且具有控制信号以控制均衡电路的操作。

    Apparatus and method using volatile lock and lock-down registers and for protecting memory blocks
    7.
    发明授权
    Apparatus and method using volatile lock and lock-down registers and for protecting memory blocks 失效
    使用易失性锁定和锁定寄存器并用于保护存储器块的装置和方法

    公开(公告)号：US6154819A

    公开(公告)日：2000-11-28

    申请号：US76298

    申请日：1998-05-11

    申请人： Robert E. Larsen ,  Peter Hazen ,  Sanjay S. Talreja ,  Sandeep Guliani ,  Robert N. Hasbun ,  Collin Ong ,  Terry D. West ,  Charles Brown ,  Terry L. Kendall

    发明人： Robert E. Larsen ,  Peter Hazen ,  Sanjay S. Talreja ,  Sandeep Guliani ,  Robert N. Hasbun ,  Collin Ong ,  Terry D. West ,  Charles Brown ,  Terry L. Kendall

    IPC分类号： G06F12/14 ,  G11C16/22

    CPC分类号： G11C16/22 ,  G06F12/1433

    摘要： An apparatus for protecting memory blocks in a block-based flash Erasable Programmable Read Only Memory (EPROM) device is disclosed. A non-volatile memory array includes a number of blocks that are capable of being placed in a locked state or an unlocked state. A volatile lock register and transmits a write protect signal and a volatile lock-down register are coupled to a lockable block in the volatile memory array. A hardware override line is coupled to both the lock register and the lock-down register. The hardware override line temporarily overrides operation of the lock-down register when it transmits a signal at a first logic state. The lock down register may be used to prevent programming of an associated lock register. The lock registers and lock down registers may be embodied in static access memory (SRAM) circuits. A command buffer may be operable to transmit a two cycle command including a first command specifying whether a lock configuration is to be changed and a second command specifying whether a block is to be placed in a lock state, an unlock state, or locked down state. The lock down registers may be capable of being set to lock down only once during a period in which the apparatus is powered up.

    摘要翻译： 公开了一种用于保护基于块的闪存可擦除可编程只读存储器（EPROM）装置中的存储块的装置。 非易失性存储器阵列包括能够被置于锁定状态或解锁状态的多个块。 易失性锁定寄存器和发送写保护信号和易失性锁存寄存器耦合到易失性存储器阵列中的可锁定块。 硬件覆盖线耦合到锁定寄存器和锁定寄存器。 当硬件覆盖线在第一逻辑状态下发送信号时，临时地覆盖锁定寄存器的操作。 锁定寄存器可用于防止相关锁定寄存器的编程。 锁定寄存器和锁定寄存器可以体现在静态存取存储器（SRAM）电路中。 命令缓冲器可以用于发送包括指定是否要改变锁定配置的第一命令和指定是否将块置于锁定状态，解锁状态或锁定状态的第二命令的两周期命令 。 锁定寄存器可能能够在设备通电期间被设置为仅锁定一次。

    Load for non-volatile memory drain bias
    8.
    发明授权
    Load for non-volatile memory drain bias 有权
    负载用于非易失性存储器漏极偏置

    公开(公告)号：US06570789B2

    公开(公告)日：2003-05-27

    申请号：US09752535

    申请日：2000-12-29

    申请人： Ritesh Trivedi ,  Robert Baltar ,  Mark Bauer ,  Sandeep Guliani ,  Balaji Srinivasan

    发明人： Ritesh Trivedi ,  Robert Baltar ,  Mark Bauer ,  Sandeep Guliani ,  Balaji Srinivasan

    IPC分类号： G11C1606

    CPC分类号： G11C16/28 ,  G11C16/24

    摘要： An apparatus is disclosed for providing a load for a non-volatile memory drain bias circuit. Under an embodiment, a load for a non-volatile memory drain bias circuit comprises a column load and a current mirror, a reference voltage for the current mirror being a sample and hold voltage reference. The column load and the current mirror are coupled to a cascode device.

    摘要翻译： 公开了一种用于为非易失性存储器漏极偏置电路提供负载的装置。 在一个实施例中，用于非易失性存储器漏极偏置电路的负载包括列负载和电流镜，电流镜的参考电压是采样和保持电压基准。 列负载和电流镜耦合到共源共栅器件。