公开(公告)号：US6154819A

公开(公告)日：2000-11-28

申请号：US76298

申请日：1998-05-11

申请人： Robert E. Larsen ,  Peter Hazen ,  Sanjay S. Talreja ,  Sandeep Guliani ,  Robert N. Hasbun ,  Collin Ong ,  Terry D. West ,  Charles Brown ,  Terry L. Kendall

发明人： Robert E. Larsen ,  Peter Hazen ,  Sanjay S. Talreja ,  Sandeep Guliani ,  Robert N. Hasbun ,  Collin Ong ,  Terry D. West ,  Charles Brown ,  Terry L. Kendall

IPC分类号： G06F12/14 ,  G11C16/22

CPC分类号： G11C16/22 ,  G06F12/1433

摘要： An apparatus for protecting memory blocks in a block-based flash Erasable Programmable Read Only Memory (EPROM) device is disclosed. A non-volatile memory array includes a number of blocks that are capable of being placed in a locked state or an unlocked state. A volatile lock register and transmits a write protect signal and a volatile lock-down register are coupled to a lockable block in the volatile memory array. A hardware override line is coupled to both the lock register and the lock-down register. The hardware override line temporarily overrides operation of the lock-down register when it transmits a signal at a first logic state. The lock down register may be used to prevent programming of an associated lock register. The lock registers and lock down registers may be embodied in static access memory (SRAM) circuits. A command buffer may be operable to transmit a two cycle command including a first command specifying whether a lock configuration is to be changed and a second command specifying whether a block is to be placed in a lock state, an unlock state, or locked down state. The lock down registers may be capable of being set to lock down only once during a period in which the apparatus is powered up.

摘要翻译： 公开了一种用于保护基于块的闪存可擦除可编程只读存储器（EPROM）装置中的存储块的装置。 非易失性存储器阵列包括能够被置于锁定状态或解锁状态的多个块。 易失性锁定寄存器和发送写保护信号和易失性锁存寄存器耦合到易失性存储器阵列中的可锁定块。 硬件覆盖线耦合到锁定寄存器和锁定寄存器。 当硬件覆盖线在第一逻辑状态下发送信号时，临时地覆盖锁定寄存器的操作。 锁定寄存器可用于防止相关锁定寄存器的编程。 锁定寄存器和锁定寄存器可以体现在静态存取存储器（SRAM）电路中。 命令缓冲器可以用于发送包括指定是否要改变锁定配置的第一命令和指定是否将块置于锁定状态，解锁状态或锁定状态的第二命令的两周期命令 。 锁定寄存器可能能够在设备通电期间被设置为仅锁定一次。

公开(公告)号：US06223290B1

公开(公告)日：2001-04-24

申请号：US09074475

申请日：1998-05-07

申请人： Robert E. Larsen ,  Peter K. Hazen ,  Sandeep K. Guliani ,  Robert N. Hasbun ,  Sanjay S. Talreja ,  Collin Ong ,  Charles W. Brown ,  Terry L. Kendall

发明人： Robert E. Larsen ,  Peter K. Hazen ,  Sandeep K. Guliani ,  Robert N. Hasbun ,  Sanjay S. Talreja ,  Collin Ong ,  Charles W. Brown ,  Terry L. Kendall

IPC分类号： H04B116

CPC分类号： H04W12/12 ,  H04W88/02

摘要： A method and apparatus for controlling use of an electronic system is described. Use of the electronic system is controlled by programming at least one unique code into an auxiliary memory of the electronic system. The auxiliary memory is a permanently lockable memory that is located outside of a main memory array space. The unique code is compared to at least one component code. Use of the electronic system is controlled based on a predefined relationship between the unique code and the component code.

摘要翻译： 描述了一种用于控制电子系统的使用的方法和装置。 通过将至少一个唯一代码编程到电子系统的辅助存储器中来控制电子系统的使用。 辅助存储器是位于主存储器阵列空间外部的永久可锁存储器。 将唯一代码与至少一个组件代码进行比较。 基于唯一代码和组件代码之间的预定关系来控制电子系统的使用。

公开(公告)号：US06401160B1

公开(公告)日：2002-06-04

申请号：US09282598

申请日：1999-03-31

申请人： Deborah L. See ,  Robert N. Hasbun

发明人： Deborah L. See ,  Robert N. Hasbun

IPC分类号： G06F1206

CPC分类号： G06F12/0223 ,  G06F12/0246 ,  G06F2212/7204 ,  G06F2212/7206

摘要： A method of moving a boundary in a nonvolatile memory is disclosed. The method comprises identifying a boundary location in the nonvolatile memory. The boundary location comprises a position between a first block of a first type and a second block of a second type. The method also comprises allocating objects from a last block of the first type to a second block of the first type. Additionally, the method comprises erasing the last block of the first type.

摘要翻译： 公开了一种在非易失性存储器中移动边界的方法。 该方法包括识别非易失性存储器中的边界位置。 边界位置包括第一类型的第一块和第二类型的第二块之间的位置。 该方法还包括将对象从第一类型的最后块分配到第一类型的第二块。 另外，该方法包括擦除第一类型的最后一个块。

公开(公告)号：US5875477A

公开(公告)日：1999-02-23

申请号：US577742

申请日：1995-12-22

申请人： Robert N. Hasbun ,  Daniel H. Leemann

发明人： Robert N. Hasbun ,  Daniel H. Leemann

IPC分类号： G06F11/10 ,  G11C29/00 ,  G06F12/16 ,  G06F11/08

CPC分类号： G11C29/765 ,  G06F11/1068

摘要： A method of accessing a memory includes the step of partitioning the memory into a plurality of partitions. A primary logical identifier is stored in the memory to identify each partition. A redundant secondary logical identifier is also stored in the memory to identify each partition. In response to a requested partition number identifying a partition to access, at least one partition of data is located using a first stored logical identifier formed from a portion of each of the primary and secondary logical identifiers. The at least one partition of data is then identified using a second stored logical identifier formed from a portion of at least one of the primary and secondary logical identifiers. In one embodiment, a first error detection code (EDC) stored in the header is used to validate the partition data. If an error is detected, the validity of the partition data is tested using an EDC computed by ANDing the first EDC and a second EDC stored in the header. During a clean-up operation, a header is selected from a block targeted for clean-up. The first and second stored logical identifiers in the selected header are compared with each other. If there is not a match, then validation is performed using the ANDed value of the first and second stored logical sector number. In one embodiment, the memory is a flash electrically erasable programmable read only memory. In one embodiment, the partitions are sectors and the identifiers are sector numbers.

摘要翻译： 访问存储器的方法包括将存储器分割成多个分区的步骤。 主逻辑标识符存储在存储器中以识别每个分区。 冗余辅助逻辑标识符也存储在存储器中以识别每个分区。 响应于识别要访问的分区的所请求的分区号，使用从每个主逻辑标识符和辅助逻辑标识符的一部分形成的第一存储的逻辑标识符来定位至少一个数据分区。 然后使用从主逻辑标识符和次逻辑标识符中的至少一个的一部分形成的第二存储的逻辑标识符来识别数据的至少一个分区。 在一个实施例中，存储在报头中的第一错误检测码（EDC）用于验证分区数据。 如果检测到错误，则使用通过对存储在报头中的第一EDC和第二EDC进行AND运算的EDC来测试分区数据的有效性。 在清理操作期间，从用于清理的块中选择一个标题。 将所选择的报头中的第一和第二存储逻辑标识符彼此进行比较。 如果不匹配，则使用第一和第二存储的逻辑扇区号的ANDed值来执行验证。 在一个实施例中，存储器是闪存电可擦除可编程只读存储器。 在一个实施例中，分区是扇区，标识符是扇区号。

公开(公告)号：US5822781A

公开(公告)日：1998-10-13

申请号：US969131

申请日：1992-10-30

申请人： Steven Wells ,  Robert N. Hasbun ,  Kurt Robinson

发明人： Steven Wells ,  Robert N. Hasbun ,  Kurt Robinson

IPC分类号： G06F3/06 ,  G06F3/08 ,  G06F12/00 ,  G06F12/02 ,  G11C16/02 ,  G06F12/04

CPC分类号： G06F3/0688 ,  G06F12/0246 ,  G06F3/0625 ,  G06F3/0626 ,  G06F3/064 ,  Y02B60/1225 ,  Y02B60/1246

摘要： A solid state memory disk that stores data on a sector basis is described. The solid state disk includes an array of FLASH memory devices, which store the sectors of data. Each block of memory within the FLASH array includes data space for storing many sectors of data and a block sector translation table. The block sector translation table identifies each sector of data stored in the block's data space by a sector number. The solid state disk also includes a controller. Among its many responsibilities, the controller manages the writing of sector data into the array and the reading of sectors of data from the array. The controller responds to a write request by seeking an earlier version of the sector which has a logical sector number equal to the sector's sector number and marking that sector dirty. Afterward, the controller allocates free memory space for the sector of data. The sector of data is then written into the allocated memory space. The controller reads sectors of data by seeking a sector header translation table to convert sector numbers into physical addresses.

摘要翻译： 描述了以扇区为基础存储数据的固态存储盘。 固态盘包括存储数据扇区的闪存存储器件阵列。 FLASH阵列内的每个存储块包括用于存储许多数据扇区的数据空间和块扇区转换表。 块扇区转换表通过扇区号识别存储在块的数据空间中的数据的每个扇区。 固态盘还包括控制器。 在其许多职责中，控制器管理将阵列数据写入阵列和从阵列读取数据的扇区。 控制器通过寻找具有等于扇区扇区号的逻辑扇区号并标记扇区脏的扇区的较早版本来响应写请求。 之后，控制器为数据扇区分配空闲的空间。 然后将数据扇区写入分配的存储空间。 控制器通过寻找扇区头转换表来将扇区号转换为物理地址来读取数据扇区。

公开(公告)号：US5765002A

公开(公告)日：1998-06-09

申请号：US938398

申请日：1997-09-26

申请人： Richard P. Garner ,  Robert N. Hasbun

发明人： Richard P. Garner ,  Robert N. Hasbun

IPC分类号： G06F1/32

CPC分类号： G06F1/3275 ,  G06F1/32 ,  Y02B60/1225 ,  Y02B60/1228

摘要： A flash electrically-erasable programmable read only memory (EEPROM) device including a flash EEPROM array having circuitry for controlling operations within the flash EEPROM array, a microprocessor for controlling operations external to the flash EEPROM array, circuitry for detecting when operations are taking place within the array, and circuitry for disabling the microprocessor during periods in which operations are taking place in the flash EEPROM array so that power use by the microprocessor is minimized.

摘要翻译： 闪存电可擦除可编程只读存储器（EEPROM）装置，其包括具有用于控制闪存EEPROM阵列内的操作的电路的快闪EEPROM阵列，用于控制闪速EEPROM阵列外部的操作的微处理器，用于检测何时在 该阵列以及用于在闪存EEPROM阵列中进行操作的周期期间禁止微处理器的电路，使得由微处理器使用的功率最小化。

公开(公告)号：US5740349A

公开(公告)日：1998-04-14

申请号：US481927

申请日：1995-06-07

申请人： Robert N. Hasbun ,  Steven E. Wells

发明人： Robert N. Hasbun ,  Steven E. Wells

IPC分类号： G11C29/00 ,  G06F11/00

CPC分类号： G11C29/765

摘要： A controller for controlling associated circuitry which includes a microprocessor, read only memory for storing control processes to be run by the microprocessor for controlling the associated circuitry, random access memory, and means for accessing the associated circuitry, by a process which detects changes in the associated circuitry during operation of the associated circuitry, and writes those changes to the read only memory so that they are available to the controller should power be lost during the operation of the associated circuitry.

摘要翻译： 一种用于控制相关电路的控制器，其包括微处理器，只读存储器，用于存储由微处理器运行的控制过程，用于控制相关联的电路，随机存取存储器和用于访问相关电路的装置，该过程检测 并且将这些改变写入只读存储器，使得它们对于控制器可用，在相关电路的操作期间应该丢失电源。

公开(公告)号：US5448577A

公开(公告)日：1995-09-05

申请号：US969464

申请日：1992-10-30

申请人： Steven E. Wells ,  Robert N. Hasbun

发明人： Steven E. Wells ,  Robert N. Hasbun

IPC分类号： G06F11/10 ,  H03M13/09 ,  H03M13/00

CPC分类号： G06F11/1068 ,  H03M13/09

摘要： A method for utilizing a cyclical redundancy check value with an identification field stored in memory which is constantly changing between testing of the cyclical redundancy check value. In order to allow the use of a cyclical redundancy check value with a field which constantly varies as does the field in a flash EEPROM memory array, various portions of the field are masked to the cyclical redundancy check and additional reliability checks are utilized to assure that those portions which are masked remain reliable.

摘要翻译： 一种用于利用存储在存储器中的识别字段的循环冗余校验值的方法，所述识别字段在循环冗余校验值的测试之间不断变化。 为了允许使用具有与闪存EEPROM存储器阵列中的字段不断变化的字段的循环冗余校验值，该字段的各个部分被掩蔽到循环冗余校验，并且使用附加的可靠性检查来确保 那些被屏蔽的部分保持可靠。

公开(公告)号：US5357475A

公开(公告)日：1994-10-18

申请号：US969466

申请日：1992-10-30

申请人： Robert N. Hasbun ,  Steven E. Wells ,  Richard P. Garner

发明人： Robert N. Hasbun ,  Steven E. Wells ,  Richard P. Garner

IPC分类号： G11C16/10 ,  G11C16/16 ,  G11C29/00 ,  G11C11/34

CPC分类号： G11C16/16 ,  G11C16/102 ,  Y10S707/99953 ,  Y10S707/99957

摘要： A process for releasing sectors of a flash EEPROM memory array which includes a plurality of individually erasable blocks and stores sectors of data in such blocks with a header providing a logical sector number, an indication of validity of data stored, and an indication of whether data is stored with the header. The process includes the steps of finding the header of a sector with data to be released, setting the indication of validity of the data stored to indicate that the data is invalid, and writing a new header for the sector to a new position in the array without data and with an indication that data is not attached.

摘要翻译： 一种用于释放快闪EEPROM存储器阵列的扇区的过程，其包括多个单独可擦除块，并且在这种块中存储具有提供逻辑扇区号的报头，存储的数据的有效性的指示以及数据的指示 与标题一起存储。 该过程包括以下步骤：用要发布的数据找出扇区的头部，设置存储的数据的有效性的指示，以指示数据无效，以及将扇区的新头部写入阵列中的新位置 没有数据，并且没有附加数据的指示。

公开(公告)号：US07389425B2

公开(公告)日：2008-06-17

申请号：US10867472

申请日：2004-06-14

申请人： Robert N. Hasbun ,  John P. Brizek ,  James R. Vogt

发明人： Robert N. Hasbun ,  John P. Brizek ,  James R. Vogt

IPC分类号： H04K1/00 ,  H04L9/00

CPC分类号： G07C9/00158 ,  G06F21/32 ,  G06F21/86 ,  G06K9/00973

摘要： A biometric-based security circuit in which the user database, processor, and biometric map generation functions are all located on the same integrated circuit whose secure contents are inaccessible from external to the integrated circuit. Biometric data, such as a fingerprint, retina scan, or voiceprint, is taken from a user requesting access to restricted resources. The biometric data is transferred into the integrated circuit, where it is converted to a biometric map and compared with a database of biometric maps stored in a non-volatile memory in the integrated circuit. The stored maps represent pre-authorized users, and a match triggers the security circuit to send a signal to a host processor authorizing the host processor to permit the requesting user access to the restricted resources. The integrated circuit essentially serves as a write-only memory for the secure data, because the secure data and security functions in the integrated circuit are not directly accessible through any pin or port, and therefore cannot be read or monitored through a dedicated security attack. A second non-volatile memory, accessible from external to the integrated circuit, can also be provided in the integrated circuit for holding non-secure data. This second memory has its own interface port, and is isolated from the security-related functions and memory so that secure and non-secure functions are physically isolated from each other and cannot be modified to overcome that isolation.

摘要翻译： 一种基于生物识别的安全电路，其中用户数据库，处理器和生物特征图生成功能都位于其集成电路的外部不可访问的相同集成电路上。 从请求访问受限资源的用户获取诸如指纹，视网膜扫描或声纹的生物特征数据。 将生物特征数据传送到集成电路中，并将其转换为生物统计图并与存储在集成电路中的非易失性存储器中的生物特征图的数据库进行比较。 存储的映射表示预授权用户，并且匹配触发安全电路向主处理器发送信号，授权主处理器允许请求用户访问受限资源。 集成电路基本上用作安全数据的只写存储器，因为集成电路中的安全数据和安全功能不能通过任何引脚或端口直接访问，因此不能通过专门的安全攻击进行读取或监视。 在集成电路中还可以提供从集成电路的外部可访问的第二非易失性存储器，用于保持非安全数据。 该第二个内存具有自己的接口端口，与安全相关的功能和内存隔离开来，使得安全和非安全的功能彼此物理隔离，不能被修改以克服隔离。