公开(公告)号：US09326371B2

公开(公告)日：2016-04-26

申请号：US12207897

申请日：2008-09-10

申请人： Sandor T. Farkas ,  Girish K. Singh

发明人： Sandor T. Farkas ,  Girish K. Singh

IPC分类号： H05K1/11 ,  H05K1/02 ,  H05K3/42

CPC分类号： H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/09781

摘要： An information handling system includes a printed circuit board (PCB) including a signal path with a trace coupled to a source, another trace coupled to a load, a tuned stub, and a via connecting the traces and the tuned stub. A method includes providing a signal path on a PCB with a trace coupled to a source, a trace coupled to a load, a tuned stub, and a via connecting the traces and the tuned stub, driving a signal on the signal path, and adjusting the tuned stub length so that the signal is unchanged between the source and the load. A PCB includes a signal path between a source and a load with two traces and a via, and a tuned path between the source and the load with the two traces, another trace, and the via, the length of the tuned path being a half wavelength stub.

摘要翻译： 信息处理系统包括印刷电路板（PCB），其包括具有耦合到源的迹线的信号路径，耦合到负载的另一迹线，调谐短截线以及连接迹线和调谐短截线的通路。 一种方法包括在PCB上提供信号路径，其具有耦合到源极的迹线，耦合到负载的迹线，调谐短截线以及连接迹线和调谐短截线的通路，驱动信号路径上的信号，以及调整 调整短线长度，使源和负载之间的信号不变。 PCB包括源和具有两个迹线和通孔的负载之间的信号路径，以及通过两条迹线，另一条迹线和通路在源极和负载之间的调谐路径，调谐路径的长度为半 波长短线

公开(公告)号：US20080062897A1

公开(公告)日：2008-03-13

申请号：US11520326

申请日：2006-09-13

申请人： John Loffink ,  Sandor T. Farkas

发明人： John Loffink ,  Sandor T. Farkas

IPC分类号： H04L5/14

CPC分类号： H04L5/1492

摘要： A time division multiplexed communication bus is disclosed that provides a low latency, low pin count solution for communications among information handling systems. The time division multiplexed serial bus is advantageous in providing communications among modular computing systems, passthrough modules and chassis management controllers, as part of a modular computing system chassis.

摘要翻译： 公开了一种时分复用通信总线，其为信息处理系统之间的通信提供低延迟，低引脚数解决方案。 作为模块化计算系统机箱的一部分，时分复用串行总线有利于在模块化计算系统，直通模块和机箱管理控制器之间提供通信。

公开(公告)号：US07848232B2

公开(公告)日：2010-12-07

申请号：US11520326

申请日：2006-09-13

申请人： John Loffink ,  Sandor T. Farkas

发明人： John Loffink ,  Sandor T. Farkas

IPC分类号： H04L12/28 ,  H04L12/43

CPC分类号： H04L5/1492

摘要： A time division multiplexed communication bus is disclosed that provides a low latency, low pin count solution for communications among information handling systems. The time division multiplexed serial bus is advantageous in providing communications among modular computing systems, passthrough modules and chassis management controllers, as part of a modular computing system chassis.

摘要翻译： 公开了一种时分复用通信总线，其为信息处理系统之间的通信提供低延迟，低引脚数解决方案。 作为模块化计算系统机箱的一部分，时分复用串行总线有利于在模块化计算系统，直通模块和机箱管理控制器之间提供通信。

公开(公告)号：US09514076B2

公开(公告)日：2016-12-06

申请号：US12131196

申请日：2008-06-02

申请人： Sandor T. Farkas ,  Fernando Meschino ,  Thomas Edwin Garvens ,  Michael Jon Roberts ,  Scott Michael Ramsey ,  Charles L. Haley

发明人： Sandor T. Farkas ,  Fernando Meschino ,  Thomas Edwin Garvens ,  Michael Jon Roberts ,  Scott Michael Ramsey ,  Charles L. Haley

IPC分类号： H05K7/10 ,  G06F13/38

CPC分类号： G06F13/385

摘要： An information handling system is set forth which includes a fully connected 4S topology that can also be populated with two processors and two link modules (e.g., two passive “slugs”) to implement a fully connected 2S topology. More specifically, the link module is a printed circuit board that implements a loopback connection between certain links of the architecture. In certain embodiment, the link module includes no electrical components. The link module merely includes a set of electrical connections (e.g., copper traces) connecting pads (e.g., gold plated pads) on a thick printed circuit board (PCB) dielectric material that is shaped to fit the processor socket. The link module is used to carry user data when the information handling system is configured in a 2S topology. The link module includes proper lane assignment that allows the module to be passive without performance reduction.

摘要翻译： 提出了一种信息处理系统，其包括完全连接的4S拓扑，其也可以用两个处理器和两个链路模块（例如，两个无源“段”）填充以实现完全连接的2S拓扑。 更具体地，链路模块是在架构的某些链路之间实现环回连接的印刷电路板。 在某些实施例中，链路模块不包括电气部件。 连接模块仅包括在厚的印刷电路板（PCB）电介质材料上连接焊盘（例如，镀金焊盘）的一组电连接（例如，铜迹线），其被成形为适合处理器插座。 链路模块用于在2S拓扑中配置信息处理系统时携带用户数据。 链路模块包括适当的通道分配，允许模块被动而不降低性能。

公开(公告)号：US07676920B2

公开(公告)日：2010-03-16

申请号：US11549869

申请日：2006-10-16

申请人： Sandor T. Farkas ,  Hector F. Martinez ,  Bhavesh Patel ,  Indrani Paul ,  Larry P. Robison, Jr. ,  Darrell J. Slupek ,  Aubrey Sparkman

发明人： Sandor T. Farkas ,  Hector F. Martinez ,  Bhavesh Patel ,  Indrani Paul ,  Larry P. Robison, Jr. ,  Darrell J. Slupek ,  Aubrey Sparkman

IPC分类号： H01K3/10 ,  G01R31/02

CPC分类号： H05K3/0047 ,  H05K1/0237 ,  H05K1/0268 ,  H05K3/429 ,  H05K2203/0207 ,  H05K2203/0242 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A test coupon on a printed circuit board used for verifying that vias in the printed circuit board are back drilled to a proper predetermined depth. Use of the coupon involves correlating a via on the board to a via of a test coupon drilling the board via and the test coupon via to substantially the same depth, where the depth is predetermined based on the board via. Then measuring the impedance of the test coupon to reveal the actual depth of the back drilling of the coupon via. Knowing the actual back drill depth of the coupon via is used to verify the back drill depth of the board via.

摘要翻译： 用于验证印刷电路板中的通孔的印刷电路板上的测试试样被回到适当的预定深度。 使用优惠券包括将电路板上的通孔与通过电路板通孔的测试券和测试券通过基本相同的深度相关联，其中深度基于板通孔预定。 然后测量试样的阻抗，以显示试样通孔背面钻孔的实际深度。 了解优惠券通道的实际后钻深度用于验证板通孔的后钻深度。

公开(公告)号：US20090296359A1

公开(公告)日：2009-12-03

申请号：US12131196

申请日：2008-06-02

申请人： Sandor T. Farkas ,  Fernando Meschino ,  Thomas Edwin Garvens ,  Michael Jon Roberts ,  Scott Michael Ramsey ,  Charles L. Haley

发明人： Sandor T. Farkas ,  Fernando Meschino ,  Thomas Edwin Garvens ,  Michael Jon Roberts ,  Scott Michael Ramsey ,  Charles L. Haley

IPC分类号： H05K7/10

CPC分类号： G06F13/385

摘要： An information handling system is set forth which includes a fully connected 4S topology that can also be populated with two processors and two link modules (e.g., two passive “slugs”) to implement a fully connected 2S topology. More specifically, the link module is a printed circuit board that implements a loopback connection between certain links of the architecture. In certain embodiment, the link module includes no electrical components. The link module merely includes a set of electrical connections (e.g., copper traces) connecting pads (e.g., gold plated pads) on a thick printed circuit board (PCB) dielectric material that is shaped to fit the processor socket. The link module is used to carry user data when the information handling system is configured in a 2S topology. The link module includes proper lane assignment that allows the module to be passive without performance reduction.

摘要翻译： 提出了一种信息处理系统，其包括完全连接的4S拓扑，其也可以用两个处理器和两个链路模块（例如，两个无源“段”）填充以实现完全连接的2S拓扑。 更具体地，链路模块是在架构的某些链路之间实现环回连接的印刷电路板。 在某些实施例中，链路模块不包括电气部件。 连接模块仅包括在厚的印刷电路板（PCB）电介质材料上连接焊盘（例如，镀金焊盘）的一组电连接（例如，铜迹线），其被成形为适合处理器插座。 链路模块用于在2S拓扑中配置信息处理系统时携带用户数据。 链路模块包括适当的通道分配，允许模块被动而不降低性能。

公开(公告)号：US08484399B2

公开(公告)日：2013-07-09

申请号：US11176989

申请日：2005-07-08

申请人： Stuart A. Berke ,  Sandor T. Farkas ,  Mukund P. Khatri

发明人： Stuart A. Berke ,  Sandor T. Farkas ,  Mukund P. Khatri

IPC分类号： H05K7/00 ,  G06F3/00 ,  G06F13/40

CPC分类号： G06F13/4022

摘要： A system and method for configuring expansion bus links to generate a double-bandwidth link slot are disclosed. An information handling system includes a central processing unit (CPU) and memory operable to store program instructions executable by the CPU. A chip set operably couples the CPU and the memory to a first slot and a second slot. The chipset includes a root port that generates a first link coupled to the first slot and a second link coupled to the second slot. An adapter card is inserted into either of the first or second slots such that the adapter card routes either the first or second link to the slot not populated by the adapter card.

摘要翻译： 公开了一种用于配置扩展总线链路以生成双带宽链路时隙的系统和方法。 信息处理系统包括中央处理单元（CPU）和可操作以存储可由CPU执行的程序指令的存储器。 芯片组将CPU和存储器可操作地耦合到第一槽和第二槽。 芯片组包括根端口，其生成耦合到第一时隙的第一链路和耦合到第二时隙的第二链路。 适配器卡被插入到第一或第二插槽中的任一个中，使得适配器卡将第一或第二链路路由到未由适配器卡填充的插槽。

公开(公告)号：US20100064180A1

公开(公告)日：2010-03-11

申请号：US12207897

申请日：2008-09-10

申请人： Sandor T. Farkas ,  Girish K. Singh

发明人： Sandor T. Farkas ,  Girish K. Singh

IPC分类号： G06F11/07

CPC分类号： H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/09781

摘要： An information handling system includes a printed circuit board (PCB) including a signal path with a trace coupled to a source, another trace coupled to a load, a tuned stub, and a via connecting the traces and the tuned stub. A method includes providing a signal path on a PCB with a trace coupled to a source, a trace coupled to a load, a tuned stub, and a via connecting the traces and the tuned stub, driving a signal on the signal path, and adjusting the tuned stub length so that the signal is unchanged between the source and the load. A PCB includes a signal path between a source and a load with two traces and a via, and a tuned path between the source and the load with the two traces, another trace, and the via, the length of the tuned path being a half wavelength stub.

摘要翻译： 信息处理系统包括印刷电路板（PCB），其包括具有耦合到源的迹线的信号路径，耦合到负载的另一迹线，调谐短截线以及连接迹线和调谐短截线的通路。 一种方法包括在PCB上提供信号路径，其具有耦合到源极的迹线，耦合到负载的迹线，调谐短截线以及连接迹线和调谐短截线的通路，驱动信号路径上的信号，以及调整 调整短线长度，使源和负载之间的信号不变。 PCB包括源和具有两个迹线和通孔的负载之间的信号路径，以及通过两条迹线，另一条迹线和通路在源极和负载之间的调谐路径，调谐路径的长度为半 波长短线

公开(公告)号：US07669071B2

公开(公告)日：2010-02-23

申请号：US11381926

申请日：2006-05-05

申请人： Stephen D. Cochran ,  Sandor T. Farkas ,  Akkiah Maddukuri

发明人： Stephen D. Cochran ,  Sandor T. Farkas ,  Akkiah Maddukuri

IPC分类号： G06F1/00 ,  G06F11/30

CPC分类号： G06F1/263 ,  G06F1/3203

摘要： An information handling system includes modular processing resources, each having a main processor, system memory, and preferably a service processor resource. A management resource coupled to a service processor resource evaluates a system power budget and allocates power to a processing resource by indicating a critical power level. The processing resource determines a warning power level based on the critical power level and monitor its actual power consumption. If actual power consumption exceeds the critical power level, the processing resource is powered down. If actual power consumption exceeds the warning power level, the processing resource throttles its performance to conserve power and requests a power allocation increase. If actual power consumption is below the warning power level, the processing resource may request a reduction in allocated power.

摘要翻译： 信息处理系统包括模块化处理资源，每个处理资源具有主处理器，系统存储器，优选地是服务处理器资源。 耦合到服务处理器资源的管理资源评估系统功率预算，并通过指示临界功率电平为处理资源分配功率。 处理资源根据临界功率电平确定警告功率电平并监视其实际功耗。 如果实际功耗超过临界功率级别，则处理资源掉电。 如果实际功耗超过警告功率级别，处理资源将节省电力并节省功率分配。 如果实际功率消耗低于警告功率电平，则处理资源可以请求降低分配的功率。

公开(公告)号：US07343227B1

公开(公告)日：2008-03-11

申请号：US11514009

申请日：2006-08-31

申请人： Paul T. Artman ,  Sandor T. Farkas

发明人： Paul T. Artman ,  Sandor T. Farkas

IPC分类号： G06F19/00 ,  G05D23/00

CPC分类号： H05K1/0201 ,  G06F1/206 ,  H05K2201/09727 ,  H05K2201/10151 ,  H05K2203/1115 ,  Y02D10/16

摘要： An information handling system including a system fan control for maintaining operating temperatures of electronics within the information handling system is disclosed. The information handling system can include a power trace provided in association with a power circuit that can power electronics within the information handling system. The power trace can include a reduced trace width region that may be operable to provide a temperature differential in response to a current change within the reduced trace width region. A thermistor may be provided in close proximity to the reduced trace width region and can be operable to detect the temperature differential provided in response to the current change. The thermistor may provide an input to a fan controller that may be operable to alter a fan speed to maintain an operating temperature of the electronics that may be coupled to the power trace.

摘要翻译： 公开了一种信息处理系统，其包括用于维护信息处理系统内的电子设备的操作温度的系统风扇控制。 信息处理系统可以包括与可以为信息处理系统内的电子设备供电的电力电路相关联地提供的电力轨迹。 功率迹线可以包括减小的迹线宽度区域，其可以可操作以响应于减小的迹线宽度区域内的电流变化来提供温度差。 可以将热敏电阻设置在靠近减小的迹线宽度区域并且可操作以检测响应于当前变化而提供的温度差。 热敏电阻可以向风扇控制器提供输入，风扇控制器可以可操作以改变风扇速度，以维持可耦合到电力轨迹的电子器件的工作温度。