公开(公告)号：US06271705B1

公开(公告)日：2001-08-07

申请号：US09448534

申请日：1999-11-22

申请人： Young-Ho Suh ,  Choong-Keun Kwak ,  Sang-Jib Han

发明人： Young-Ho Suh ,  Choong-Keun Kwak ,  Sang-Jib Han

IPC分类号： H03K500

CPC分类号： H01L27/0266

摘要： A data output circuit includes a periphery circuit connected between a supply voltage and a first ground voltage line and an output driver connected between a supply voltage and a second ground voltage line. The periphery circuit receives a first input signal and generates a first output signal on a node responsive to the first input signal, and the output driver receives a second input signal and the first output signal and generates a second output signal on an output pin in response thereto. A discharge circuit is coupled with the first ground voltage line wherein the discharge circuit allows current to flow from the first ground voltage line and wherein the discharge circuit blocks current flow to the first ground voltage line. Related methods are also discussed.

摘要翻译： 数据输出电路包括连接在电源电压和第一接地电压线之间的外围电路以及连接在电源电压和第二接地电压线之间的输出驱动器。 外围电路接收第一输入信号并响应于第一输入信号在节点上产生第一输出信号，并且输出驱动器接收第二输入信号和第一输出信号，并响应于输出引脚产生第二输出信号 到此。 放电电路与第一接地电压线耦合，其中放电电路允许电流从第一接地电压线流出，并且其中放电电路阻止电流流到第一接地电压线。 还讨论了相关方法。

公开(公告)号：US5994943A

公开(公告)日：1999-11-30

申请号：US963792

申请日：1997-11-04

申请人： Young-Ho Suh ,  Choong-Keun Kwak ,  Sang-Jib Han

发明人： Young-Ho Suh ,  Choong-Keun Kwak ,  Sang-Jib Han

IPC分类号： G11C11/417 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H03K19/003 ,  H03K19/0175 ,  H03H5/00 ,  H02H3/20

CPC分类号： H01L27/0266

摘要： A data output circuit includes a periphery circuit connected between a supply voltage and a first ground voltage line and an output driver connected between a supply voltage and a second ground voltage line. The periphery circuit receives a first input signal and generates a first output signal on a node responsive to the first input signal, and the output driver receives a second input signal and the first output signal and generates a second output signal on an output pin in response thereto. A discharge circuit is coupled with the first ground voltage line wherein the discharge circuit allows current to flow from the first ground voltage line and wherein the discharge circuit blocks current flow to the first ground voltage line. Related methods are also discussed.

摘要翻译： 数据输出电路包括连接在电源电压和第一接地电压线之间的外围电路以及连接在电源电压和第二接地电压线之间的输出驱动器。 外围电路接收第一输入信号并响应于第一输入信号在节点上产生第一输出信号，并且输出驱动器接收第二输入信号和第一输出信号，并响应于输出引脚产生第二输出信号 到此。 放电电路与第一接地电压线耦合，其中放电电路允许电流从第一接地电压线流出，并且其中放电电路阻止电流流到第一接地电压线。 还讨论了相关方法。

公开(公告)号：US06288926B1

公开(公告)日：2001-09-11

申请号：US09535871

申请日：2000-03-27

申请人： Du-Eung Kim ,  Byung-Gil Choi ,  Sang-Jib Han ,  Choong-Keun Kwak ,  Soon-Moon Jung ,  Sung-Bong Kim

发明人： Du-Eung Kim ,  Byung-Gil Choi ,  Sang-Jib Han ,  Choong-Keun Kwak ,  Soon-Moon Jung ,  Sung-Bong Kim

IPC分类号： G11C506

CPC分类号： G11C5/063 ,  G11C11/412

摘要： A semiconductor memory device is disclosed. The device is comprised of a plurality of word lines; a plurality of bit lines arranged in perpendicular to the word lines. In addition, a plurality of supply voltage lines extend in the same direction as the bit lines. Also, a plurality of first ground voltage lines are arranged in the same direction as the bit lines. Further, a plurality of second ground voltage lines are arranged in the same direction as the word lines. A plurality of memory cells are each connected between one of the word lines and one of the bit lines. Here, the ground voltage lines are arranged in a matrix shape to reduce the resistance of the ground voltage line and secure the margin between the supply voltage level and the ground voltage level of the data latched by the memory cells to thereby prevent an operational failure of the device.

摘要翻译： 公开了一种半导体存储器件。 该装置由多条字线组成; 垂直于字线布置的多个位线。 此外，多个电源电压线沿与位线相同的方向延伸。 此外，多个第一接地电压线被布置在与位线相同的方向上。 此外，多个第二接地电压线布置在与字线相同的方向上。 多个存储单元分别连接在一条字线和一条位线之间。 这里，接地电压线被布置成矩阵形状以减小接地电压线的电阻并且确保由存储器单元锁存的数据的电源电压电平和接地电压电平之间的裕度，从而防止 装置。

公开(公告)号：US06256254B1

公开(公告)日：2001-07-03

申请号：US09564593

申请日：2000-05-03

申请人： Choong-Keun Kwak ,  Sang-Jib Han

发明人： Choong-Keun Kwak ,  Sang-Jib Han

IPC分类号： G11C800

CPC分类号： G11C8/12 ,  G11C8/10

摘要： A semiconductor memory device includes a plurality of memory cell array blocks, an address transition detecting pulse generator to generate address transition detecting pulse signals by detecting the transition of a plurality of addresses, a global row decoder having a plurality of groups of pre-decoders and a main decoder to generate a plurality of global word line signals of a plurality of memory cell array blocks by decoding the plurality of addresses, and a plurality of block row decoders having a plurality of decoding cells to respond to block control signals for selecting a plurality of memory cell array blocks and a plurality of pulse control signals combined with the address transition detecting pulse signals to output a plurality of global word line signals generated by the global row decoder as a plurality of local word line signals. A plurality of the decoding cells of a plurality of the block row decoders comprises switching transistors or other means to switch the global word line signals into local word line signals in response to a first state of the pulse control signals, and inactive means, e.g. one or more transistors, to put the local word line signals into its inactive state in response to a second state of the pulse control signals, thereby reducing the number of transistors to make up of the decoder for efficient layout.

摘要翻译： 半导体存储器件包括多个存储单元阵列块，地址转换检测脉冲发生器，用于通过检测多个地址的转换来产生地址转换检测脉冲信号;全局行解码器，具有多组预解码器;以及 主解码器，用于通过解码多个地址来生成多个存储单元阵列块的多个全局字线信号;以及多个块行解码器，具有多个解码单元，以响应用于选择多个地址的块控制信号 的存储单元阵列块和与地址转换检测脉冲信号组合的多个脉冲控制信号，以将由全局行解码器产生的多个全局字线信号作为多个本地字线信号输出。 多个块行解码器的多个解码单元包括开关晶体管或其他装置，以响应于脉冲控制信号的第一状态将全局字线信号切换为本地字线信号，以及无效装置，例如， 一个或多个晶体管，以响应于脉冲控制信号的第二状态将本地字线信号置于其非活动状态，从而减少用于有效布局的解码器的晶体管数量。

公开(公告)号：US20060104102A1

公开(公告)日：2006-05-18

申请号：US11183613

申请日：2005-07-18

申请人： Byung-Gil Choi ,  Young-Ho Suh ,  Choong-Keun Kwak

发明人： Byung-Gil Choi ,  Young-Ho Suh ,  Choong-Keun Kwak

IPC分类号： G11C5/06

CPC分类号： G11C7/02 ,  G11C7/18

摘要： A true bit line can extend across a memory cell area of the memory device in a first direction and a complementary bit line can extend across the memory cell area in a second direction opposing the first direction, wherein the true bit line and the complementary bit line comprising a bit line pair.

摘要翻译： 真正的位线可以沿第一方向跨越存储器件的存储器单元区域延伸，并且互补位线可以在与第一方向相反的第二方向跨越存储器单元区域延伸，其中真位线和互补位线 包括位线对。

公开(公告)号：US07426129B2

公开(公告)日：2008-09-16

申请号：US11183613

申请日：2005-07-18

申请人： Byung-Gil Choi ,  Young-Ho Suh ,  Choong-Keun Kwak

发明人： Byung-Gil Choi ,  Young-Ho Suh ,  Choong-Keun Kwak

IPC分类号： G11C5/06

CPC分类号： G11C7/02 ,  G11C7/18

摘要： A true bit line can extend across a memory cell area of the memory device in a first direction and a complementary bit line can extend across the memory cell area in a second direction opposing the first direction, wherein the true bit line and the complementary bit line comprising a bit line pair.

摘要翻译： 真正的位线可以沿第一方向跨越存储器件的存储器单元区域延伸，并且互补位线可以在与第一方向相反的第二方向跨越存储器单元区域延伸，其中真位线和互补位线 包括位线对。

公开(公告)号：US5754487A

公开(公告)日：1998-05-19

申请号：US749277

申请日：1996-11-13

申请人： Du-Eung Kim ,  Choong-Keun Kwak ,  Young-Ho Suh ,  Hyun-Geun Byun

发明人： Du-Eung Kim ,  Choong-Keun Kwak ,  Young-Ho Suh ,  Hyun-Geun Byun

IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C7/12

摘要： An SRAM, which includes a plurality of bit line pairs, a memory cell connected between each pair of the bit lines, and an address transition detection circuit for detecting transition of the externally applied address signal to generate a detection pulse signal, is provided with an improved bit line precharge circuit requiring only two transistors per bit line pair. The new precharge circuit is controlled by a bit line precharge control signal generator for generating a control signal determined by a ratio of impedances connected between a source voltage and ground voltage.

摘要翻译： 包括多个位线对的SRAM，连接在每对位线之间的存储单元，以及用于检测外部施加的地址信号的转换以产生检测脉冲信号的地址转换检测电路， 改进的位线预充电电路每位线对只需要两个晶体管。 新的预充电电路由位线预充电控制信号发生器控制，用于产生由源电压和接地电压之间连接的阻抗比确定的控制信号。

公开(公告)号：US07796425B2

公开(公告)日：2010-09-14

申请号：US11985975

申请日：2007-11-19

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

IPC分类号： G11C11/00 ,  G11C7/04 ,  G11C11/4193 ,  G11C11/4197

CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C2013/0078

摘要： A driver circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the pulse width for higher peripheral temperature.

摘要翻译： 用于PRAM（相变随机存取存储器）装置的驱动器电路包括响应于置位/复位脉冲而产生置位/复位电流的写入驱动器。 此外，温度补偿器响应于PRAM器件的外围温度来控制置位/复位脉冲的脉冲宽度。 例如，温度补偿器将脉冲宽度保持为基本恒定，而与外围温度无关。 在另一个例子中，温度补偿器降低脉冲宽度，以提高外围温度。

公开(公告)号：US20080212362A1

公开(公告)日：2008-09-04

申请号：US11985975

申请日：2007-11-19

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C2013/0078

摘要： A driver circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the pulse width for higher peripheral temperature.

摘要翻译： 用于PRAM（相变随机存取存储器）装置的驱动器电路包括响应于置位/复位脉冲而产生置位/复位电流的写入驱动器。 此外，温度补偿器响应于PRAM器件的外围温度来控制置位/复位脉冲的脉冲宽度。 例如，温度补偿器将脉冲宽度保持为基本恒定，而与外围温度无关。 在另一个例子中，温度补偿器降低脉冲宽度，以提高外围温度。

公开(公告)号：US07315469B2

公开(公告)日：2008-01-01

申请号：US11124341

申请日：2005-05-06

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Woo-Yeong Cho

IPC分类号： G11C11/00 ,  G11C7/04 ,  G11C7/22

CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C2013/0078

摘要： A drive circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the width for higher peripheral temperature.

摘要翻译： 用于PRAM（相变随机存取存储器）装置的驱动电路包括响应于置位/复位脉冲而产生置位/复位电流的写入驱动器。 此外，温度补偿器响应于PRAM器件的外围温度来控制置位/复位脉冲的脉冲宽度。 例如，温度补偿器将脉冲宽度保持为基本恒定，而与外围温度无关。 在另一个例子中，温度补偿器减小了较高外围温度的宽度。