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    Data transfer circuit and method with compensated clock jitter
    1.
    发明授权
    Data transfer circuit and method with compensated clock jitter 有权
    具有补偿时钟抖动的数据传输电路和方法

    公开(公告)号：US08497718B2

    公开(公告)日：2013-07-30

    申请号：US13613342

    申请日：2012-09-13

    申请人： Seung Jun Bae ,  Kwang Il Park ,  Young-Sik Kim ,  Sang Hyup Kwak

    发明人： Seung Jun Bae ,  Kwang Il Park ,  Young-Sik Kim ,  Sang Hyup Kwak

    IPC分类号： H03L7/00

    CPC分类号： H03K5/1565 ,  H03K2005/0013

    摘要： A data I/O interface for an integrated circuit device includes a noise detector receiving a power supply voltage, detecting a power supply voltage noise component, and providing a clock delay control signal in response to detected power supply voltage noise component. The data I/O interface also includes a clock delay circuit providing a delayed clock signal in response to the clock delay control signal, and a data transfer circuit powered by the power supply voltage and providing output data synchronously with the delayed clock signal.

    摘要翻译： 用于集成电路装置的数据I / O接口包括接收电源电压的噪声检测器，检测电源电压噪声分量，以及响应于检测到的电源电压噪声分量提供时钟延迟控制信号。 数据I / O接口还包括响应于时钟延迟控制信号提供延迟时钟信号的时钟延迟电路和由电源电压供电并且与延迟的时钟信号同步地提供输出数据的数据传输电路。

    Semiconductor memory device comprising variable delay unit
    2.
    发明授权
    Semiconductor memory device comprising variable delay unit 有权
    半导体存储器件包括可变延迟单元

    公开(公告)号：US08339877B2

    公开(公告)日：2012-12-25

    申请号：US12764460

    申请日：2010-04-21

    申请人： Sang-Hyup Kwak ,  Seung-Jun Bae ,  Young-Sik Kim

    发明人： Sang-Hyup Kwak ,  Seung-Jun Bae ,  Young-Sik Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/4401 ,  G11C29/50012 ,  G11C2207/2254

    摘要： A semiconductor memory device comprises a variable delay unit and a data trainer. The variable delay unit is configured to generate a write data signal by delaying a write data driving signal by different amounts of time depending on whether the semiconductor memory device is in a data training mode or a normal operating mode, and further configured to generate a read data driving signal by delaying a read data signal by different amounts of time in the data training mode and the normal operating mode. The data trainer is configured to be activated in the data training mode, and while activated, receive the write data signal, compare the write data signal with a predetermined write pattern, perform a data training mode operation, and output the read data signal with a predetermined read pattern.

    摘要翻译： 半导体存储器件包括可变延迟单元和数据训练器。 可变延迟单元被配置为根据半导体存储器件是处于数据训练模式还是正常操作模式，通过将写入数据驱动信号延迟不同的时间量来产生写入数据信号，并且还被配置为产生读取 数据驱动信号，通过在数据训练模式和正常操作模式下延迟读取数据信号不同的时间量。 数据训练器被配置为在数据训练模式下被激活，并且被激活时，接收写入数据信号，将写入数据信号与预定的写入模式进行比较，执行数据训练模式操作，并将读出的数据信号输出 预定的读取模式。

    VOLTAGE-CONTROLLED OSCILLATOR AND PHASE-LOCKED LOOP CIRCUIT
    3.
    发明申请
    VOLTAGE-CONTROLLED OSCILLATOR AND PHASE-LOCKED LOOP CIRCUIT 有权
    电压控制振荡器和相位锁定环路

    公开(公告)号：US20110310659A1

    公开(公告)日：2011-12-22

    申请号：US13109157

    申请日：2011-05-17

    申请人： Ho-Seok Seol ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    发明人： Ho-Seok Seol ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    IPC分类号： G11C11/24 ,  H03B5/12 ,  H03B7/06

    CPC分类号： H03B5/1228 ,  G11C7/222 ,  H03B5/1215 ,  H03B5/124

    摘要： A voltage-controlled oscillator includes an oscillating unit configured to output first and second output clock signals at first and second nodes, respectively, the first and second output clock signals having a frequency that is variable in response to a control voltage. An active element unit connected to the oscillating unit is configured to maintain oscillation of the oscillating unit. A bias current generating unit connected to the active element unit at a bias node provides a bias current to the bias node and is adapted to adjust the bias current in response to a control code. First and second capacitor blocks connected to the oscillating unit and the active element unit provide first and second load capacitances, respectively, to the first and second nodes, respectively, in response to the control code.

    摘要翻译： 压控振荡器包括：振荡单元，被配置为分别在第一和第二节点处输出第一和第二输出时钟信号，第一和第二输出时钟信号具有响应于控制电压而变化的频率。 连接到振荡单元的有源元件单元被配置为保持振荡单元的振荡。 在偏置节点处连接到有源元件单元的偏置电流产生单元向偏置节点提供偏置电流，并且适于响应于控制代码调整偏置电流。 连接到振荡单元和有源元件单元的第一和第二电容器块分别响应于控制代码分别向第一和第二节点提供第一和第二负载电容。

    Phase-Locked Loop and Bias Generator
    4.
    发明申请
    Phase-Locked Loop and Bias Generator 有权
    锁相环和偏置发生器

    公开(公告)号：US20100141311A1

    公开(公告)日：2010-06-10

    申请号：US12627730

    申请日：2009-11-30

    申请人： Young-Sik Kim ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    发明人： Young-Sik Kim ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    IPC分类号： H03L7/06 ,  H03K3/01

    CPC分类号： H03L7/08

    摘要： A phase-locked loop (PLL) having a bias generator capable of reducing noise is provided. In the PLL, a voltage controlled oscillator is driven using a regulator. The bias generator, which applies a bias voltage to the regulator, is configured to have opposite power noise characteristics to the power noise characteristics of the regulator, such that the occurrence of jitter in the PLL is reduced.

    摘要翻译： 提供了具有能够降低噪声的偏置发生器的锁相环（PLL）。 在PLL中，使用稳压器驱动压控振荡器。 将偏置电压施加到调节器的偏置发生器被配置为具有与调节器的功率噪声特性相反的功率噪声特性，使得PLL中的抖动的发生减少。

    Data mask system and data mask method
    5.
    发明授权
    Data mask system and data mask method 有权
    数据掩码系统和数据掩码法

    公开(公告)号：US08321640B2

    公开(公告)日：2012-11-27

    申请号：US12780986

    申请日：2010-05-17

    申请人： Sang-hyup Kwak ,  Kwang-il Park ,  Seung-jun Bae

    发明人： Sang-hyup Kwak ,  Kwang-il Park ,  Seung-jun Bae

    IPC分类号： G06F12/00

    CPC分类号： G11C7/1078 ,  G11C7/1006 ,  G11C11/4096

    摘要： A data mask system includes a processor providing control signals including a command signal, an address signal, and a data signal, a data mask processor receiving the control signals and providing either write data or masked data in response to the control signals, and generating data mask information and a data mask selection signal from at least one of the control signals, and a data mask register unit receiving the data mask selection signal, storing the data mask information, selecting a subset of the stored data mask information in response to the data mask selection signal, and returning selected data mask information to the data mask processor. The data mask processor receives the selected data mask information from the data mask register unit and provides the masked data as a result of performing a data mask operation on the data signal according to the selected data mask information.

    摘要翻译： 数据掩模系统包括提供包括命令信号，地址信号和数据信号的控制信号的处理器，接收控制信号的数据掩码处理器，并响应于控制信号提供写数据或屏蔽数据，并产生数据 来自至少一个控制信号的掩模信息和数据掩模选择信号，以及接收数据掩码选择信号的数据掩码寄存器单元，存储数据掩码信息，响应于数据选择存储的数据掩码信息的子集 掩模选择信号，并将选择的数据掩码信息返回到数据掩码处理器。 数据掩模处理器从数据掩码寄存器单元接收所选择的数据掩码信息，并根据所选择的数据掩码信息提供作为数据信号的数据掩码操作的结果的掩蔽数据。

    Data transfer circuit and method with compensated clock jitter
    6.
    发明授权
    Data transfer circuit and method with compensated clock jitter 有权
    具有补偿时钟抖动的数据传输电路和方法

    公开(公告)号：US08269537B2

    公开(公告)日：2012-09-18

    申请号：US12754794

    申请日：2010-04-06

    申请人： Seung Jun Bae ,  Kwang II Park ,  Young-Sik Kim ,  Sang Hyup Kwak

    发明人： Seung Jun Bae ,  Kwang II Park ,  Young-Sik Kim ,  Sang Hyup Kwak

    IPC分类号： H03L7/00

    CPC分类号： H03K5/1565 ,  H03K2005/0013

    摘要： A data I/O interface for an integrated circuit device includes a noise detector receiving a power supply voltage, detecting a power supply voltage noise component, and providing a clock delay control signal in response to detected power supply voltage noise component. The data I/O interface also includes a clock delay circuit providing a delayed clock signal in response to the clock delay control signal, and a data transfer circuit powered by the power supply voltage and providing output data synchronously with the delayed clock signal.

    摘要翻译： 用于集成电路装置的数据I / O接口包括接收电源电压的噪声检测器，检测电源电压噪声分量，以及响应于检测到的电源电压噪声分量提供时钟延迟控制信号。 数据I / O接口还包括响应于时钟延迟控制信号提供延迟时钟信号的时钟延迟电路和由电源电压供电并且与延迟的时钟信号同步地提供输出数据的数据传输电路。

    Phase-locked loop and bias generator
    7.
    发明授权
    Phase-locked loop and bias generator 有权
    锁相环和偏置发生器

    公开(公告)号：US08159275B2

    公开(公告)日：2012-04-17

    申请号：US12627730

    申请日：2009-11-30

    申请人： Young-Sik Kim ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    发明人： Young-Sik Kim ,  Seung-Jun Bae ,  Sang-Hyup Kwak

    IPC分类号： H03L7/06

    CPC分类号： H03L7/08

    摘要： A phase-locked loop (PLL) having a bias generator capable of reducing noise is provided. In the PLL, a voltage controlled oscillator is driven using a regulator. The bias generator, which applies a bias voltage to the regulator, is configured to have opposite power noise characteristics to the power noise characteristics of the regulator, such that the occurrence of jitter in the PLL is reduced.

    摘要翻译： 提供了具有能够降低噪声的偏置发生器的锁相环（PLL）。 在PLL中，使用稳压器驱动压控振荡器。 将偏置电压施加到调节器的偏置发生器被配置为具有与调节器的功率噪声特性相反的功率噪声特性，使得PLL中的抖动的发生减少。

    DATA MASK SYSTEM AND DATA MASK METHOD
    8.
    发明申请
    DATA MASK SYSTEM AND DATA MASK METHOD 有权
    数据掩码系统和数据掩码方法

    公开(公告)号：US20110030064A1

    公开(公告)日：2011-02-03

    申请号：US12780986

    申请日：2010-05-17

    申请人： Sang-hyup KWAK ,  Kwang-il PARK ,  Seung-jun BAE

    发明人： Sang-hyup KWAK ,  Kwang-il PARK ,  Seung-jun BAE

    IPC分类号： G06F12/14 ,  G11C7/00 ,  G06F12/00

    CPC分类号： G11C7/1078 ,  G11C7/1006 ,  G11C11/4096

    摘要： A data mask system includes a processor providing control signals including a command signal, an address signal, and a data signal, a data mask processor receiving the control signals and providing either write data or masked data in response to the control signals, and generating data mask information and a data mask selection signal from at least one of the control signals, and a data mask register unit receiving the data mask selection signal, storing the data mask information, selecting a subset of the stored data mask information in response to the data mask selection signal, and returning selected data mask information to the data mask processor. The data mask processor receives the selected data mask information from the data mask register unit and provides the masked data as a result of performing a data mask operation on the data signal according to the selected data mask information.

    摘要翻译： 数据掩模系统包括提供包括命令信号，地址信号和数据信号的控制信号的处理器，接收控制信号的数据掩码处理器，并响应于控制信号提供写数据或屏蔽数据，并产生数据 来自至少一个控制信号的掩模信息和数据掩模选择信号，以及接收数据掩码选择信号的数据掩码寄存器单元，存储数据掩码信息，响应于数据选择存储的数据掩码信息的子集 掩模选择信号，并将选择的数据掩码信息返回到数据掩码处理器。 数据掩模处理器从数据掩码寄存器单元接收所选择的数据掩码信息，并根据所选择的数据掩码信息提供作为数据信号的数据掩码操作的结果的掩蔽数据。

    BIDIRECTIONAL EQUALIZER WITH CMOS INDUCTIVE BIAS CIRCUIT
    9.
    发明申请
    BIDIRECTIONAL EQUALIZER WITH CMOS INDUCTIVE BIAS CIRCUIT 有权
    具有CMOS感应偏置电路的双向均衡器

    公开(公告)号：US20110026334A1

    公开(公告)日：2011-02-03

    申请号：US12832212

    申请日：2010-07-08

    申请人： Seung-jun BAE ,  Young-sik KIM ,  Sang-hyup KWAK

    发明人： Seung-jun BAE ,  Young-sik KIM ,  Sang-hyup KWAK

    IPC分类号： G11C7/00 ,  H03K19/003

    CPC分类号： G11C7/1078 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1084 ,  H03K19/018521

    摘要： An integrated circuit (IC) device, system and related method of communicating data are described. The IC device includes; a data port configured to provide output data to a channel and receive input data from the channel, an impedance matching circuit connected to the data port and configured to operate as an output driver circuit when the output data is being transmitted and as an on die termination circuit when the input data is being received, and an active inductive bias circuit connected to the data port in parallel with the impedance matching circuit, and configured to adjust the impedance of the data port to the channel during transmission of the output data as a function of output data frequency and adjust the impedance of the data port to the channel during receipt of the input data as a function of input data frequency.

    摘要翻译： 描述了一种用于传送数据的集成电路（IC）装置，系统和相关方法。 IC器件包括： 数据端口，被配置为向通道提供输出数据并从所述通道接收输入数据;阻抗匹配电路，连接到所述数据端口，并且被配置为当所述输出数据被发送时作为输出驱动器电路工作，并且作为管芯端接 接收输入数据时的电路以及与阻抗匹配电路并联连接到数据端口的有源感应偏置电路，并且被配置为在输出数据作为功能的传输期间调整数据端口到通道的阻抗 的输出数据频率，并根据输入数据频率调整输入数据接收期间数据端口到通道的阻抗。

    SEMICONDUCTOR MEMORY DEVICE COMPRISING VARIABLE DELAY UNIT
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE COMPRISING VARIABLE DELAY UNIT 有权
    包含可变延迟单元的半导体存储器件

    公开(公告)号：US20100271887A1

    公开(公告)日：2010-10-28

    申请号：US12764460

    申请日：2010-04-21

    申请人： Sang-Hyup KWAK ,  Seung-Jun BAE ,  Young-Sik KIM

    发明人： Sang-Hyup KWAK ,  Seung-Jun BAE ,  Young-Sik KIM

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/4401 ,  G11C29/50012 ,  G11C2207/2254

    摘要： A semiconductor memory device comprises a variable delay unit and a data trainer. The variable delay unit is configured to generate a write data signal by delaying a write data driving signal by different amounts of time depending on whether the semiconductor memory device is in a data training mode or a normal operating mode, and further configured to generate a read data driving signal by delaying a read data signal by different amounts of time in the data training mode and the normal operating mode. The data trainer is configured to be activated in the data training mode, and while activated, receive the write data signal, compare the write data signal with a predetermined write pattern, perform a data training mode operation, and output the read data signal with a predetermined read pattern.

    摘要翻译： 半导体存储器件包括可变延迟单元和数据训练器。 可变延迟单元被配置为根据半导体存储器件是处于数据训练模式还是正常操作模式，通过将写入数据驱动信号延迟不同的时间量来产生写入数据信号，并且还被配置为产生读取 数据驱动信号，通过在数据训练模式和正常操作模式下延迟读取数据信号不同的时间量。 数据训练器被配置为在数据训练模式下被激活，并且被激活时，接收写入数据信号，将写入数据信号与预定的写入模式进行比较，执行数据训练模式操作，并将读出的数据信号输出 预定的读取模式。