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    INPUT/OUTPUT (IO) INTERFACE AND METHOD OF TRANSMITTING IO DATA
    1.
    发明申请
    INPUT/OUTPUT (IO) INTERFACE AND METHOD OF TRANSMITTING IO DATA 失效
    输入/输出（IO）接口和传输IO数据的方法

    公开(公告)号：US20100045491A1

    公开(公告)日：2010-02-25

    申请号：US12547204

    申请日：2009-08-25

    申请人： Seung-jun Bae ,  Young-hyun Jun ,  Joo-sun Choi ,  Kwang-il Park ,  Sang-hyup Kwak

    发明人： Seung-jun Bae ,  Young-hyun Jun ,  Joo-sun Choi ,  Kwang-il Park ,  Sang-hyup Kwak

    IPC分类号： H03M7/00

    CPC分类号： H03M5/06 ,  G11C7/1006

    摘要： An input/output (IO) interface includes a data encoder which encodes each of a plurality of pieces of parallel data having different timings and generates a plurality of pieces of encoded data, and an alternating current (AC) coupling transmission unit which transmits the plurality of encoded data in an AC coupling method. The data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains the number of bits whose logic states have transited between the first parallel data and the second parallel data. When the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data. When the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data.

    摘要翻译： 输入/输出（IO）接口包括数据编码器，其对具有不同定时的多个并行数据中的每一个进行编码并生成多个编码数据;以及交流（AC）耦合传输单元，其传输多个 的交流耦合方法中的编码数据。 数据编码器在逐位的基础上将第一并行数据与多条并行数据中的第二并行数据进行比较，并且获得其逻辑状态已经在第一并行数据和第二并行数据之间转移的位数。 当逻辑状态已经转移的位数大于或等于参考位数时，数据编码器反转第二并行数据的位值，以产生编码数据。 当逻辑状态已经转移的位数小于参考位数时，数据编码器维持第二并行数据的位值以产生编码数据。

    Input/output (IO) interface and method of transmitting IO data
    2.
    发明授权
    Input/output (IO) interface and method of transmitting IO data 失效
    输入/输出（IO）接口和传输IO数据的方法

    公开(公告)号：US07986251B2

    公开(公告)日：2011-07-26

    申请号：US12547204

    申请日：2009-08-25

    申请人： Seung-jun Bae ,  Young-hyun Jun ,  Joo-sun Choi ,  Kwang-il Park ,  Sang-hyup Kwak

    发明人： Seung-jun Bae ,  Young-hyun Jun ,  Joo-sun Choi ,  Kwang-il Park ,  Sang-hyup Kwak

    IPC分类号： H03M5/00

    CPC分类号： H03M5/06 ,  G11C7/1006

    摘要： An input/output (IO) interface includes a data encoder which encodes each of a plurality of pieces of parallel data having different timings and generates a plurality of pieces of encoded data, and an alternating current (AC) coupling transmission unit which transmits the plurality of encoded data in an AC coupling method. The data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains the number of bits whose logic states have transited between the first parallel data and the second parallel data. When the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data. When the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data.

    摘要翻译： 输入/输出（IO）接口包括数据编码器，其对具有不同定时的多条并行数据中的每一条进行编码并产生多条编码数据;以及交流（AC）耦合传输单元，其传输多个 的交流耦合方法中的编码数据。 数据编码器在逐位的基础上将第一并行数据与多条并行数据中的第二并行数据进行比较，并且获得其逻辑状态已经在第一并行数据和第二并行数据之间转移的位数。 当逻辑状态已经转移的位数大于或等于参考位数时，数据编码器反转第二并行数据的位值，以产生编码数据。 当逻辑状态已经转移的位数小于参考位数时，数据编码器维持第二并行数据的位值以产生编码数据。

    Data mask system and data mask method
    3.
    发明授权
    Data mask system and data mask method 有权
    数据掩码系统和数据掩码法

    公开(公告)号：US08321640B2

    公开(公告)日：2012-11-27

    申请号：US12780986

    申请日：2010-05-17

    申请人： Sang-hyup Kwak ,  Kwang-il Park ,  Seung-jun Bae

    发明人： Sang-hyup Kwak ,  Kwang-il Park ,  Seung-jun Bae

    IPC分类号： G06F12/00

    CPC分类号： G11C7/1078 ,  G11C7/1006 ,  G11C11/4096

    摘要： A data mask system includes a processor providing control signals including a command signal, an address signal, and a data signal, a data mask processor receiving the control signals and providing either write data or masked data in response to the control signals, and generating data mask information and a data mask selection signal from at least one of the control signals, and a data mask register unit receiving the data mask selection signal, storing the data mask information, selecting a subset of the stored data mask information in response to the data mask selection signal, and returning selected data mask information to the data mask processor. The data mask processor receives the selected data mask information from the data mask register unit and provides the masked data as a result of performing a data mask operation on the data signal according to the selected data mask information.

    摘要翻译： 数据掩模系统包括提供包括命令信号，地址信号和数据信号的控制信号的处理器，接收控制信号的数据掩码处理器，并响应于控制信号提供写数据或屏蔽数据，并产生数据 来自至少一个控制信号的掩模信息和数据掩模选择信号，以及接收数据掩码选择信号的数据掩码寄存器单元，存储数据掩码信息，响应于数据选择存储的数据掩码信息的子集 掩模选择信号，并将选择的数据掩码信息返回到数据掩码处理器。 数据掩模处理器从数据掩码寄存器单元接收所选择的数据掩码信息，并根据所选择的数据掩码信息提供作为数据信号的数据掩码操作的结果的掩蔽数据。

    Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods
    4.
    发明授权
    Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods 有权
    实现时钟镜像方案和相关内存系统的内存设备和时钟镜像方法

    公开(公告)号：US07814239B2

    公开(公告)日：2010-10-12

    申请号：US12045289

    申请日：2008-03-10

    申请人： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    发明人： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    IPC分类号： G06F3/00

    CPC分类号： G11C5/063 ,  G06F1/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4076 ,  G11C2207/105

    摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

    摘要翻译： 存储器件被配置为在第一和第二数据输入/输出模式下操作。 存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。 时钟信号线被配置为将时钟传送到存储器件内部的集成电路。 第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。 第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。

    Linear digital phase interpolator and semi-digital delay locked loop (DLL)
    5.
    发明授权
    Linear digital phase interpolator and semi-digital delay locked loop (DLL) 有权
    线性数字相位插值器和半数字延迟锁定环（DLL）

    公开(公告)号：US07772907B2

    公开(公告)日：2010-08-10

    申请号：US12255170

    申请日：2008-10-21

    申请人： Jin-gook Kim ,  Seung-jun Bae ,  Kwang-il Park

    发明人： Jin-gook Kim ,  Seung-jun Bae ,  Kwang-il Park

    IPC分类号： H03H3/00 ,  H03K5/13

    CPC分类号： H03L7/0814 ,  H03L7/07

    摘要： Provided are a digital phase interpolator, which performs linear phase interpolation irrelevantly to input order of two input signals, and a semi-digital delay locked loop (DLL), which includes and controls the same. The phase interpolator includes: a first clocked inverter controlled by a phase indicating signal and providing a first output signal to a common output terminal by inverting a first input signal, and a second clocked inverter controlled by the phase indicating signal and providing a second output signal to the common output terminal by inverting the second input signal. The second clocked inverter is clocked by the first input signal when the phase indicating signal is in a first logic state, and the first clocked inverter is clocked by the second input signal when the phase indicating signal is in a second logic state. The phase indicating signal indicates a lead/lag phase relationship between the first and second input signals and is generated in a controller of a circuit of the semi-digital DLL.

    摘要翻译： 提供了一种数字相位内插器，其执行与两个输入信号的输入顺序无关的线性相位插值和包括并控制相同的半数字延迟锁定环（DLL）。 相位插值器包括：由相位指示信号控制的第一时钟反相器，并通过反相第一输入信号向公共输出端提供第一输出信号;以及由相位指示信号控制的第二时钟反相器，并提供第二输出信号 通过反转第二输入信号到公共输出端子。 当相位指示信号处于第一逻辑状态时，第二时钟反相器由第一输入信号计时，当相位指示信号处于第二逻辑状态时，第一时钟反相器由第二输入信号计时。 相位指示信号表示第一和第二输入信号之间的引导/滞后相位关系，并且在半数字DLL的电路的控制器中产生。

    MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS
    7.
    发明申请
    MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS 有权
    存储器件实现时钟模式和相关的存储器系统和时钟模式

    公开(公告)号：US20110029697A1

    公开(公告)日：2011-02-03

    申请号：US12902328

    申请日：2010-10-12

    申请人： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    发明人： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    IPC分类号： G06F3/00

    CPC分类号： G11C5/063 ,  G06F1/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4076 ,  G11C2207/105

    摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

    摘要翻译： 存储器件被配置为在第一和第二数据输入/输出模式下操作。 存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。 时钟信号线被配置为将时钟传送到存储器件内部的集成电路。 第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。 第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。

    MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS
    8.
    发明申请
    MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS 有权
    存储器件实现时钟模式和相关的存储器系统和时钟模式

    公开(公告)号：US20080225623A1

    公开(公告)日：2008-09-18

    申请号：US12045289

    申请日：2008-03-10

    申请人： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    发明人： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

    IPC分类号： G11C8/00

    CPC分类号： G11C5/063 ,  G06F1/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4076 ,  G11C2207/105

    摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

    摘要翻译： 存储器件被配置为在第一和第二数据输入/输出模式下操作。 存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。 时钟信号线被配置为将时钟传送到存储器件内部的集成电路。 第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。 第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。