公开(公告)号：US07642619B2

公开(公告)日：2010-01-05

申请号：US12489773

申请日：2009-06-23

Applicant: Phillip D. Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

Inventor： Phillip D. Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

IPC: H01L29/00

CPC classification number: H01L28/10 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device, such as an inductor, is formed with an air gap. A first level has an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures. An inter-level dielectric layer is formed over the first level. An extraction via is formed through the intra-metal dielectric layer and inter-level dielectric layer. An air gap is formed between inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using a supercritical fluid process, and forming a non-conformal layer to seal the extraction via. The air gap may be filled with an inert gas, like argon or nitrogen.

Abstract translation: 诸如电感器的半导体器件形成有气隙。 第一级具有包括一个或多个电感器环，一个或多个通孔和一个或多个铜隔板结构的金属间介电层。 在第一级上形成层间电介质层。 通过金属介电层和层间电介质层形成提取孔。 通过使用超临界流体过程去除与金属介电层相连的金属介电层中的部分，形成不均匀层以密封提取孔，从而在电感器环之间形成气隙。 空气间隙可以填充惰性气体，如氩气或氮气。

公开(公告)号：US20090001510A1

公开(公告)日：2009-01-01

申请号：US11771298

申请日：2007-06-29

Applicant: Phillip D Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

Inventor： Phillip D Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

IPC: H01L29/00 ,  H01L21/02

CPC classification number: H01L28/10 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In accordance with the invention, there are inductors with an air gap, semiconductor devices, integrated circuits, and methods of fabricating them. The method of making an inductor with an air gap can include fabricating a first level of inductor in an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures, forming an inter-level dielectric layer over the first level and repeating the steps to form two or more levels of inductor. The method can also include forming an extraction via, forming an air gap between the inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using super critical fluid process, and forming a non-conformal layer to seal the extraction via.

Abstract translation: 根据本发明，具有气隙的电感器，半导体器件，集成电路及其制造方法。 制造具有气隙的电感器的方法可以包括在包括一个或多个电感器环路，一个或多个通孔以及一个或多个铜隔板结构的金属间介电层中制造第一级电感器，形成级间 电介质层，并且重复步骤以形成两个或更多级别的电感器。 该方法还可以包括形成提取通孔，通过使用超临界流体过程去除与金属介电层相连的部分金属介电层，从而在电感器环之间形成气隙，并形成非共形层以密封提取 通过。

公开(公告)号：US07115467B2

公开(公告)日：2006-10-03

申请号：US10903712

申请日：2004-07-30

Applicant: Sameer Kumar Ajmera ,  Darius L. Crenshaw ,  Stephan Grunow ,  Satyavolu S. Papa Rao ,  Phillip D. Matz

Inventor： Sameer Kumar Ajmera ,  Darius L. Crenshaw ,  Stephan Grunow ,  Satyavolu S. Papa Rao ,  Phillip D. Matz

IPC: H01L21/8242

CPC classification number: H01L28/75

Abstract: A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A layer of bottom electrode/copper diffusion barrier material (136) is formed (16) within an aperture (128) wherein the capacitor (100) is to be defined. The bottom electrode layer (136) is formed via a directional process so that a horizontal aspect (138) of the layer (136) is formed over a metal (110) at a bottom of the aperture (128) to a thickness (142) that is greater than a thickness (144) of a sidewall aspect (148) of the layer (136) formed upon sidewalls (132) of the aperture (128). Accordingly, the thinner sidewall aspects (148) are removed during an etching act (18) while some of the thicker horizontal aspect (138) remains. A layer of capacitor dielectric material (150) is then conformally formed (20) into the aperture 128 and over the horizontal aspect (138). A layer of top electrode material (152) is then conformally formed (22) over the layer of capacitor dielectric material (150) to complete the capacitor stack (154).

公开(公告)号：US07781884B2

公开(公告)日：2010-08-24

申请号：US11863477

申请日：2007-09-28

Applicant: Sameer Kumar Ajmera ,  Phillip D. Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

Inventor： Sameer Kumar Ajmera ,  Phillip D. Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

IPC: H01L23/34

CPC classification number: H01L23/427 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The density of components in integrated circuits (ICs) is increasing with time. The density of heat generated by the components is similarly increasing. Maintaining the temperature of the components at reliable operating levels requires increased thermal transfer rates from the components to the IC package exterior. Dielectric materials used in interconnect regions have lower thermal conductivity than silicon dioxide. This invention comprises a heat pipe located in the interconnect region of an IC to transfer heat generated by components in the IC substrate to metal plugs located on the top surface of the IC, where the heat is easily conducted to the exterior of the IC package. Refinements such as a wicking liner or reticulated inner surface will increase the thermal transfer efficiency of the heat pipe. Strengthening elements in the interior of the heat pipe will provide robustness to mechanical stress during IC manufacture.

Abstract translation: 集成电路（IC）中组件的密度随时间而增加。 组件产生的热密度同样增加。 将组件的温度保持在可靠的操作水平，需要增加从组件到IC封装外部的热传递速率。 互连区域中使用的介电材料的热导率低于二氧化硅。 本发明包括位于IC的互连区域中的热管，用于将IC基板中的部件产生的热量转移到位于IC顶表面上的金属插头，其中热量易于传导到IC封装的外部。 诸如芯吸衬垫或网状内表面的改进将增加热管的热传递效率。 热管内部加强元件将为IC制造过程中的机械应力提供坚固耐用性。

公开(公告)号：US20090261453A1

公开(公告)日：2009-10-22

申请号：US12489773

申请日：2009-06-23

Applicant: Phillip D. Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

Inventor： Phillip D. Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

IPC: H01L27/02

CPC classification number: H01L28/10 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device, such as an inductor, is formed with an air gap. A first level has an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures. An inter-level dielectric layer is formed over the first level. An extraction via is formed through the intra-metal dielectric layer and inter-level dielectric layer. An air gap is formed between inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using a supercritical fluid process, and forming a non-conformal layer to seal the extraction via. The air gap may be filled with an inert gas, like argon or nitrogen.

Abstract translation: 诸如电感器的半导体器件形成有气隙。 第一级具有包括一个或多个电感器环，一个或多个通孔和一个或多个铜隔板结构的金属间介电层。 在第一级上形成层间电介质层。 通过金属介电层和层间电介质层形成提取孔。 通过使用超临界流体过程去除与金属介电层相连的金属介电层中的部分，形成不均匀层以密封提取孔，从而在电感器环之间形成气隙。 空气间隙可以填充惰性气体，如氩气或氮气。

公开(公告)号：US07566627B2

公开(公告)日：2009-07-28

申请号：US11771298

申请日：2007-06-29

Applicant: Phillip D Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

Inventor： Phillip D Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

IPC: H01L21/20

CPC classification number: H01L28/10 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In accordance with the invention, there are inductors with an air gap, semiconductor devices, integrated circuits, and methods of fabricating them. The method of making an inductor with an air gap can include fabricating a first level of inductor in an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures, forming an inter-level dielectric layer over the first level and repeating the steps to form two or more levels of inductor. The method can also include forming an extraction via, forming an air gap between the inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using super critical fluid process, and forming a non-conformal layer to seal the extraction via.

Abstract translation: 根据本发明，具有气隙的电感器，半导体器件，集成电路及其制造方法。 制造具有气隙的电感器的方法可以包括在包括一个或多个电感器环路，一个或多个通孔以及一个或多个铜隔板结构的金属间介电层中制造第一级电感器，形成级间 电介质层，并且重复步骤以形成两个或更多级别的电感器。 该方法还可以包括形成提取通孔，通过使用超临界流体过程去除与金属介电层相连的部分金属介电层，从而在电感器环之间形成气隙，并形成非共形层以密封提取 通过。

公开(公告)号：US07179747B2

公开(公告)日：2007-02-20

申请号：US10902243

申请日：2004-07-28

Applicant: Satyavolu S. Papa Rao ,  Stephan Grunow ,  Phillip D. Matz

Inventor： Satyavolu S. Papa Rao ,  Stephan Grunow ,  Phillip D. Matz

IPC: H01L21/311 ,  H01L21/302

CPC classification number: H01L23/5329 ,  H01L21/31116 ,  H01L21/7682 ,  H01L21/76838 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of the invention is a method of manufacturing an integrated circuit. The method includes forming a capping layer of a back end structure (step 706), drilling an extraction line from the capping layer to an inter-metal dielectric layer (step 708), performing a supercritical fluid process to remove portions of the inter-metal dielectric layer that are coupled to the extraction line (step 710): thereby forming a denuded dielectric region. Another embodiment of the invention is an integrated circuit 2 having a back-end structure 5 coupled to a front-end structure 4. The back-end structure 5 having a first metal level 22. The first metal level 22 having metal interconnects 15 and an inter-metal dielectric layer 19. The back-end structure 5 further containing an extraction line 24 and a denuded dielectric region 25 coupled to the extraction line 24.

Abstract translation: 本发明的实施例是一种制造集成电路的方法。 该方法包括形成后端结构的覆盖层（步骤706），将覆盖层从提覆层钻到金属间介电层（步骤708），执行超临界流体处理以去除金属间的部分 电介质层，其与所述提取线耦合（步骤710）：由此形成裸露的电介质区域。 本发明的另一实施例是具有耦合到前端结构4的后端结构5的集成电路2.具有第一金属层22的后端结构5.具有金属互连15的第一金属级22和 金属间介电层19.后端结构5还包含抽出线24和耦合到提取线24的裸露介质区25。

公开(公告)号：US07067441B2

公开(公告)日：2006-06-27

申请号：US10702949

申请日：2003-11-06

Applicant: Patricia B. Smith ,  Phillip D. Matz

Inventor： Patricia B. Smith ,  Phillip D. Matz

IPC: H01L21/469

CPC classification number: H01L21/76802 ,  G03F7/427 ,  H01L21/02052 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138

Abstract: A process for removing resist (114) from a CDO dielectric material (110) that uses a non-damaging plasma in a reducing atmosphere under high power and using a structure (150) or other means to limit ions from the plasma from reaching the surface of the CDO material (110).

Abstract translation: 一种从CDO电介质材料（110）去除抗蚀剂（114）的方法，该方法在高功率下在还原气氛中使用非破坏性的等离子体，并且使用结构（150）或其它方法来限制来自等离子体的离子到达表面 的CDO材料（110）。

公开(公告)号：US20090085197A1

公开(公告)日：2009-04-02

申请号：US11863477

申请日：2007-09-28

Applicant: Sameer Kumar Ajmera ,  Phillip D. Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

Inventor： Sameer Kumar Ajmera ,  Phillip D. Matz ,  Stephan Grunow ,  Satyavolu Srinivas Papa Rao

IPC: H01L23/34

CPC classification number: H01L23/427 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The density of components in integrated circuits (ICs) is increasing with time. The density of heat generated by the components is similarly increasing. Maintaining the temperature of the components at reliable operating levels requires increased thermal transfer rates from the components to the IC package exterior. Dielectric materials used in interconnect regions have lower thermal conductivity than silicon dioxide. This invention comprises a heat pipe located in the interconnect region of an IC to transfer heat generated by components in the IC substrate to metal plugs located on the top surface of the IC, where the heat is easily conducted to the exterior of the IC package. Refinements such as a wicking liner or reticulated inner surface will increase the thermal transfer efficiency of the heat pipe. Strengthening elements in the interior of the heat pipe will provide robustness to mechanical stress during IC manufacture.

Abstract translation: 集成电路（IC）中组件的密度随时间而增加。 组件产生的热密度同样增加。 将组件的温度保持在可靠的操作水平，需要增加从组件到IC封装外部的热传递速率。 互连区域中使用的介电材料的热导率低于二氧化硅。 本发明包括位于IC的互连区域中的热管，用于将IC基板中的部件产生的热量转移到位于IC顶表面上的金属插头，其中热量易于传导到IC封装的外部。 诸如芯吸衬垫或网状内表面的改进将增加热管的热传递效率。 热管内部加强元件将为IC制造过程中的机械应力提供坚固耐用性。

公开(公告)号：US07485963B2

公开(公告)日：2009-02-03

申请号：US11614094

申请日：2006-12-21

Applicant: Satyavolu S. Papa Rao ,  Stephan Grunow ,  Phillip D. Matz

Inventor： Satyavolu S. Papa Rao ,  Stephan Grunow ,  Phillip D. Matz

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5329 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76852 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of the invention is a method of manufacturing an integrated circuit. The method includes forming a capping layer of a back end structure (step 706), drilling an extraction line from the capping layer to an inter-metal dielectric layer (step 708), performing a supercritical fluid process to remove portions of the inter-metal dielectric layer that are coupled to the extraction line (step 710): thereby forming a denuded dielectric region. Another embodiment of the invention is an integrated circuit 2 having a back-end structure 5 coupled to a front-end structure 4. The back-end structure 5 having a first metal level 22. The first metal level 22 having metal interconnects 15 and an inter-metal dielectric layer 19. The back-end structure 5 further containing an extraction line 24 and a denuded dielectric region 25 coupled to the extraction line 24.

Abstract translation: 本发明的实施例是一种制造集成电路的方法。 该方法包括形成后端结构的覆盖层（步骤706），将覆盖层从提覆层钻到金属间介电层（步骤708），执行超临界流体处理以去除金属间的部分 电介质层，其与所述提取线耦合（步骤710）：由此形成裸露的电介质区域。 本发明的另一实施例是具有耦合到前端结构4的后端结构5的集成电路2.具有第一金属层22的后端结构5.具有金属互连15的第一金属级22和 金属间介电层19.后端结构5还包含抽出线24和耦合到提取线24的裸露介质区25。