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公开(公告)号：US07566627B2
公开(公告)日：2009-07-28
申请号：US11771298
申请日：2007-06-29
IPC分类号： H01L21/20
CPC分类号： H01L28/10 , H01L21/7682 , H01L23/5222 , H01L23/5227 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： In accordance with the invention, there are inductors with an air gap, semiconductor devices, integrated circuits, and methods of fabricating them. The method of making an inductor with an air gap can include fabricating a first level of inductor in an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures, forming an inter-level dielectric layer over the first level and repeating the steps to form two or more levels of inductor. The method can also include forming an extraction via, forming an air gap between the inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using super critical fluid process, and forming a non-conformal layer to seal the extraction via.
摘要翻译： 根据本发明，具有气隙的电感器，半导体器件，集成电路及其制造方法。 制造具有气隙的电感器的方法可以包括在包括一个或多个电感器环路，一个或多个通孔以及一个或多个铜隔板结构的金属间介电层中制造第一级电感器，形成级间 电介质层，并且重复步骤以形成两个或更多级别的电感器。 该方法还可以包括形成提取通孔，通过使用超临界流体过程去除与金属介电层相连的部分金属介电层，从而在电感器环之间形成气隙，并形成非共形层以密封提取 通过。
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2.发明申请公开(公告)号：US20090085197A1
公开(公告)日：2009-04-02
申请号：US11863477
申请日：2007-09-28
IPC分类号： H01L23/34
CPC分类号： H01L23/427 , H01L2924/0002 , H01L2924/00
摘要： The density of components in integrated circuits (ICs) is increasing with time. The density of heat generated by the components is similarly increasing. Maintaining the temperature of the components at reliable operating levels requires increased thermal transfer rates from the components to the IC package exterior. Dielectric materials used in interconnect regions have lower thermal conductivity than silicon dioxide. This invention comprises a heat pipe located in the interconnect region of an IC to transfer heat generated by components in the IC substrate to metal plugs located on the top surface of the IC, where the heat is easily conducted to the exterior of the IC package. Refinements such as a wicking liner or reticulated inner surface will increase the thermal transfer efficiency of the heat pipe. Strengthening elements in the interior of the heat pipe will provide robustness to mechanical stress during IC manufacture.
摘要翻译： 集成电路（IC）中组件的密度随时间而增加。 组件产生的热密度同样增加。 将组件的温度保持在可靠的操作水平，需要增加从组件到IC封装外部的热传递速率。 互连区域中使用的介电材料的热导率低于二氧化硅。 本发明包括位于IC的互连区域中的热管，用于将IC基板中的部件产生的热量转移到位于IC顶表面上的金属插头，其中热量易于传导到IC封装的外部。 诸如芯吸衬垫或网状内表面的改进将增加热管的热传递效率。 热管内部加强元件将为IC制造过程中的机械应力提供坚固耐用性。
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3.发明授权Single mask MIM capacitor and resistor with in trench copper drift barrier 有权单掩模MIM电容器和电阻器具有沟槽铜漂移屏障公开(公告)号：US07189615B2
公开(公告)日：2007-03-13
申请号：US11037530
申请日：2005-01-18
申请人： Satyavolu Srinivas Papa Rao , Darius Lammont Crenshaw , Stephan Grunow , Kenneth D. Brennan , Somit Joshi , Montray Leavy , Phillip D. Matz , Sameer Kumar Ajmera , Yuri E. Solomentsev
发明人： Satyavolu Srinivas Papa Rao , Darius Lammont Crenshaw , Stephan Grunow , Kenneth D. Brennan , Somit Joshi , Montray Leavy , Phillip D. Matz , Sameer Kumar Ajmera , Yuri E. Solomentsev
IPC分类号： H01L21/8242
CPC分类号： H01L21/76834 , H01L21/288 , H01L21/76816 , H01L21/76849 , H01L23/5223 , H01L28/20 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The formation of a MIM (metal insulator metal) capacitor (164) and concurrent formation of a resistor (166) is disclosed. A copper diffusion barrier (124) is formed over a copper deposition (110) that serves as a bottom electrode (170) of the capacitor (164). The copper diffusion barrier (124) mitigates unwanted diffusion of copper from the copper deposition (110), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface (125) of the deposition of copper/bottom electrode. Subsequently, layers of dielectric (150) and conductive (152) materials are applied to form a dielectric (172) and top electrode (174) of the MIM capacitor (164), respectively, where the layer of conductive top electrode material (152) also functions to concurrently develop the resistor (166) on the same chip as the capacitor (164).
摘要翻译： 公开了MIM（金属绝缘金属）电容器（164）的形成和电阻器（166）的同时形成。 在用作电容器（164）的底部电极（170）的铜沉积（110）上形成铜扩散阻挡层（124）。 铜扩散阻挡层（124）减轻了铜从铜沉积物（110）的不期望的扩散，并且通过无电沉积形成，使得在除了顶部表面（125）之外的位置处几乎不会沉积阻挡材料， 的铜/底电极的沉积。 随后，分别施加介电层（150）和导电（152）材料层以形成MIM电容器（164）的电介质（172）和顶电极（174），其中导电顶电极材料层（152） 还用于同时开发与电容器（164）相同的芯片上的电阻器（166）。
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4.发明授权公开(公告)号：US07781884B2
公开(公告)日：2010-08-24
申请号：US11863477
申请日：2007-09-28
IPC分类号： H01L23/34
CPC分类号： H01L23/427 , H01L2924/0002 , H01L2924/00
摘要： The density of components in integrated circuits (ICs) is increasing with time. The density of heat generated by the components is similarly increasing. Maintaining the temperature of the components at reliable operating levels requires increased thermal transfer rates from the components to the IC package exterior. Dielectric materials used in interconnect regions have lower thermal conductivity than silicon dioxide. This invention comprises a heat pipe located in the interconnect region of an IC to transfer heat generated by components in the IC substrate to metal plugs located on the top surface of the IC, where the heat is easily conducted to the exterior of the IC package. Refinements such as a wicking liner or reticulated inner surface will increase the thermal transfer efficiency of the heat pipe. Strengthening elements in the interior of the heat pipe will provide robustness to mechanical stress during IC manufacture.
摘要翻译： 集成电路（IC）中组件的密度随时间而增加。 组件产生的热密度同样增加。 将组件的温度保持在可靠的操作水平，需要增加从组件到IC封装外部的热传递速率。 互连区域中使用的介电材料的热导率低于二氧化硅。 本发明包括位于IC的互连区域中的热管，用于将IC基板中的部件产生的热量转移到位于IC顶表面上的金属插头，其中热量易于传导到IC封装的外部。 诸如芯吸衬垫或网状内表面的改进将增加热管的热传递效率。 热管内部加强元件将为IC制造过程中的机械应力提供坚固耐用性。
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公开(公告)号：US20090261453A1
公开(公告)日：2009-10-22
申请号：US12489773
申请日：2009-06-23
IPC分类号： H01L27/02
CPC分类号： H01L28/10 , H01L21/7682 , H01L23/5222 , H01L23/5227 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device, such as an inductor, is formed with an air gap. A first level has an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures. An inter-level dielectric layer is formed over the first level. An extraction via is formed through the intra-metal dielectric layer and inter-level dielectric layer. An air gap is formed between inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using a supercritical fluid process, and forming a non-conformal layer to seal the extraction via. The air gap may be filled with an inert gas, like argon or nitrogen.
摘要翻译： 诸如电感器的半导体器件形成有气隙。 第一级具有包括一个或多个电感器环，一个或多个通孔和一个或多个铜隔板结构的金属间介电层。 在第一级上形成层间电介质层。 通过金属介电层和层间电介质层形成提取孔。 通过使用超临界流体过程去除与金属介电层相连的金属介电层中的部分，形成不均匀层以密封提取孔，从而在电感器环之间形成气隙。 空气间隙可以填充惰性气体，如氩气或氮气。
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公开(公告)号：US07642619B2
公开(公告)日：2010-01-05
申请号：US12489773
申请日：2009-06-23
IPC分类号： H01L29/00
CPC分类号： H01L28/10 , H01L21/7682 , H01L23/5222 , H01L23/5227 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device, such as an inductor, is formed with an air gap. A first level has an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures. An inter-level dielectric layer is formed over the first level. An extraction via is formed through the intra-metal dielectric layer and inter-level dielectric layer. An air gap is formed between inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using a supercritical fluid process, and forming a non-conformal layer to seal the extraction via. The air gap may be filled with an inert gas, like argon or nitrogen.
摘要翻译： 诸如电感器的半导体器件形成有气隙。 第一级具有包括一个或多个电感器环，一个或多个通孔和一个或多个铜隔板结构的金属间介电层。 在第一级上形成层间电介质层。 通过金属介电层和层间电介质层形成提取孔。 通过使用超临界流体过程去除与金属介电层相连的金属介电层中的部分，形成不均匀层以密封提取孔，从而在电感器环之间形成气隙。 空气间隙可以填充惰性气体，如氩气或氮气。
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公开(公告)号：US20090001510A1
公开(公告)日：2009-01-01
申请号：US11771298
申请日：2007-06-29
CPC分类号： H01L28/10 , H01L21/7682 , H01L23/5222 , H01L23/5227 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： In accordance with the invention, there are inductors with an air gap, semiconductor devices, integrated circuits, and methods of fabricating them. The method of making an inductor with an air gap can include fabricating a first level of inductor in an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures, forming an inter-level dielectric layer over the first level and repeating the steps to form two or more levels of inductor. The method can also include forming an extraction via, forming an air gap between the inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using super critical fluid process, and forming a non-conformal layer to seal the extraction via.
摘要翻译： 根据本发明，具有气隙的电感器，半导体器件，集成电路及其制造方法。 制造具有气隙的电感器的方法可以包括在包括一个或多个电感器环路，一个或多个通孔以及一个或多个铜隔板结构的金属间介电层中制造第一级电感器，形成级间 电介质层，并且重复步骤以形成两个或更多级别的电感器。 该方法还可以包括形成提取通孔，通过使用超临界流体过程去除与金属介电层相连的部分金属介电层，从而在电感器环之间形成气隙，并形成非共形层以密封提取 通过。
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8.发明授权公开(公告)号：US07338893B2
公开(公告)日：2008-03-04
申请号：US11286877
申请日：2005-11-23
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76844
摘要： A device employs damascene layers with a pore sealing liner and includes a semiconductor body. A metal interconnect layer comprising a metal interconnect is formed over the semiconductor body. A dielectric layer is formed over the metal interconnect layer. A conductive trench feature and a conductive via feature are formed in the dielectric layer. A pore sealing liner is formed only along sidewall of the conductive via feature and along sidewalls and bottom surfaces of the conductive trench feature. The pore sealing liner is not substantially present along a bottom surface of the conductive via feature.
摘要翻译： 装置采用具有孔密封衬垫的镶嵌层，并且包括半导体本体。 包括金属互连的金属互连层形成在半导体本体上。 介电层形成在金属互连层上。 导电沟槽特征和导电通孔特征形成在电介质层中。 孔密封衬垫仅沿着导电通孔特征的侧壁并且沿着导电沟槽特征的侧壁和底表面形成。 孔密封衬垫基本上不存在于导电通孔特征的底表面上。
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公开(公告)号：US20090166865A1
公开(公告)日：2009-07-02
申请号：US11968093
申请日：2007-12-31
CPC分类号： C23C14/0641 , C23C14/0073 , H01L21/2855 , H01L21/76843 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Devices and methods are presented to fabricate diffusion barrier layers on a substrate. Presently, barrier layers comprising a nitride layer and a pure metal layer are formed using a physical vapor deposition (PVD) process that requires multiple ignition steps, and results in nitride-layer thicknesses of no less than 2 nm. This invention discloses devices and process to produce nitride-layers of less than
摘要翻译： 提供了设备和方法来在衬底上制造扩散阻挡层。 目前，使用需要多个点火步骤的物理气相沉积（PVD）工艺形成包括氮化物层和纯金属层的阻挡层，并且导致不小于2nm的氮化物层厚度。 本发明公开了生产小于1nm的氮化物层的装置和方法，同时允许在氮化物层上形成纯金属层而不再等离子体。 为了达到这个目的，在等离子体被点燃之前或在形成连续流动等离子体之前，氮气流被切断。 这确保了有限数量的氮原子与基底上的金属原子结合沉积，从而允许氮化物层的受控厚度。
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10.发明授权公开(公告)号：US07037837B2
公开(公告)日：2006-05-02
申请号：US10903598
申请日：2004-07-29
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/76865 , H01L21/76868 , H01L21/76873
摘要： A method for fabricating a seed layer. A seed layer (126) is deposited over a barrier layer (124) using a three-step process comprising a low AC bias power step, a high AC bias power step, and a lower/zero AC bias power step. The low AC bias power step provides low overhang. The high AC bias power step provides good sidewall coverage. The lower/zero AC bias step recovers areas exposed by re-sputtering during the high AC bias power step.
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