公开(公告)号：US20100052799A1

公开(公告)日：2010-03-04

申请号：US12473317

申请日：2009-05-28

Applicant: Shinsuke Watanabe ,  Seiki Goto ,  Yoshihiro Tsukahara ,  Ko Kanaya

Inventor： Shinsuke Watanabe ,  Seiki Goto ,  Yoshihiro Tsukahara ,  Ko Kanaya

IPC: H03L7/00

CPC classification number: H03L7/099 ,  H03B5/1847

Abstract: A voltage controlled oscillator having low phase noise and including: a variable resonator including a varactor and a control voltage terminal; and an open-end stub connected in parallel to the variable resonator, the open-end stub having a length shorter than or equal to an odd multiple of one quarter of a wavelength of a harmonic signal plus one sixteenth of the wavelength of the harmonic signal, and longer than or equal to an odd multiple of one quarter of the wavelength of the harmonic signal minus one sixteenth of the wavelength of the harmonic signal. In this structure, a high Q value is realized for a fundamental wave frequency. Fluctuation in a control voltage due to a harmonic signal is controlled.

Abstract translation: 一种具有低相位噪声的压控振荡器，包括：包括变容二极管和控制电压端子的可变谐振器; 以及与可变谐振器并联连接的开路短截线，开路短截线长度短于或等于谐波信号的波长的四分之一加上谐波信号的波长的十六分之一的奇数倍 并且长于或等于谐波信号的四分之一波长的奇数倍减去谐波信号的波长的十六分之一。 在该结构中，对于基波频率实现高Q值。 控制由于谐波信号引起的控制电压的波动。

公开(公告)号：US07030698B2

公开(公告)日：2006-04-18

申请号：US10819207

申请日：2004-04-07

Applicant: Seiki Goto ,  Yoshinobu Sasaki

Inventor： Seiki Goto ,  Yoshinobu Sasaki

IPC: H03F3/68

CPC classification number: H01L29/7392 ,  H01L21/265 ,  H03F3/604

Abstract: In a high-frequency power amplifier, gate feed portions are formed by dividing a gate feed which connects transistor gate electrodes in parallel, and each of the gate feed portions includes a given number of gate electrodes connected in parallel. Each of transistor cell elements includes a set of the gate electrodes connected in parallel. A resistance wire is interposed between the transistor cell elements to isolate each transistor cell element. The resistance wire and the gate electrodes are made of the same metal material and formed by the same process. Thus, closed loop oscillation of transistors is suppressed with no increase in chip size.

Abstract translation: 在高频功率放大器中，栅极馈电部分通过分开并联连接晶体管栅电极的栅极馈电而形成，并且每个栅极馈送部分包括并联连接的给定数量的栅电极。 每个晶体管单元元件包括并联连接的一组栅电极。 电阻线插在晶体管单元元件之间以隔离每个晶体管单元元件。 电阻丝和栅电极由相同的金属材料制成并通过相同的工艺形成。 因此，晶体管的闭环振荡被抑制，芯片尺寸没有增加。

公开(公告)号：US20050007200A1

公开(公告)日：2005-01-13

申请号：US10873291

申请日：2004-06-23

Applicant: Akira Inoue ,  Seiki Goto

Inventor： Akira Inoue ,  Seiki Goto

IPC: H01L27/06 ,  H01L21/8232 ,  H01L27/095 ,  H01L29/80 ,  H03F1/22 ,  H03F3/189

CPC classification number: H03F1/223 ,  H03F3/189

Abstract: A cascode circuit includes a first field effect transistor which has a source terminal grounded, a second field effect transistor which has a source terminal connected to a drain terminal of the first field effect transistor, and a first capacitor connected between the source terminal of the first field effect transistor and a gate terminal of the second field effect transistor. The first field effect transistor and the second field effect transistor are cascode-connected successively. A capacitance value of the first capacitor is 0.01 to 10 times that between the gate and source terminals of the second field effect transistor.

Abstract translation: 共射共振电路包括：源极端子接地的第一场效应晶体管，具有与第一场效应晶体管的漏极端子连接的源极端子的第二场效应晶体管，以及连接在第一场效应晶体管的源极端子之间的第一电容器 场效应晶体管和第二场效应晶体管的栅极端子。 第一场效应晶体管和第二场效应晶体管被依次串联连接。 第一电容器的电容值是第二场效应晶体管的栅极和源极之间的电容值的0.01至10倍。

公开(公告)号：US07071786B2

公开(公告)日：2006-07-04

申请号：US10873291

申请日：2004-06-23

Applicant: Akira Inoue ,  Seiki Goto

Inventor： Akira Inoue ,  Seiki Goto

IPC: H03F3/04

CPC classification number: H03F1/223 ,  H03F3/189

Abstract: A cascode circuit includes a first field effect transistor which has a source terminal grounded, a second field effect transistor which has a source terminal connected to a drain terminal of the first field effect transistor, and a first capacitor connected between the source terminal of the first field effect transistor and a gate terminal of the second field effect transistor. The first field effect transistor and the second field effect transistor are cascode-connected successively. A capacitance value of the first capacitor is 0.01 to 10 times that between the gate and source terminals of the second field effect transistor.

Abstract translation: 共射共振电路包括：源极端子接地的第一场效应晶体管，具有与第一场效应晶体管的漏极端子连接的源极端子的第二场效应晶体管，以及连接在第一场效应晶体管的源极端子之间的第一电容器 场效应晶体管和第二场效应晶体管的栅极端子。 第一场效应晶体管和第二场效应晶体管被依次串联连接。 第一电容器的电容值是第二场效应晶体管的栅极和源极之间的电容值的0.01至10倍。

公开(公告)号：US07714664B2

公开(公告)日：2010-05-11

申请号：US12421664

申请日：2009-04-10

Applicant: Ko Kanaya ,  Seiki Goto ,  Shinsuke Watanabe

Inventor： Ko Kanaya ,  Seiki Goto ,  Shinsuke Watanabe

IPC: H03F3/04

CPC classification number: H03F1/226 ,  H03F1/0261 ,  H03F3/1935 ,  H03F2200/18 ,  H03F2200/27 ,  H03F2200/451 ,  H03F2200/534 ,  H03F2200/541

Abstract: A cascode circuit for a high-gain or high-output millimeter-wave device that operates with stability. The cascode circuit including two cascode-connected transistors includes: a first high electron mobility transistor (HEMT) including a source that is grounded; a second HEMT including a source connected to a drain of the first HEMT; a reflection gain restricting resistance connected to the gate of the second HEMT, for restricting reflection gain; and an open stub connected to a side of the reflection gain restricting resistance which is opposite the side connected to the second HEMT, for short-circuiting high-frequency signals at a predetermined frequency and nearby frequencies.

Abstract translation: 用于稳定运行的高增益或高输出毫米波器件的共源共栅电路。 包括两个共源共栅连接的晶体管的共源共栅电路包括：包括接地的源的第一高电子迁移率晶体管（HEMT）; 包括连接到第一HEMT的漏极的源的第二HEMT; 连接到第二HEMT的栅极的反射增益限制电阻，用于限制反射增益; 以及连接到反射增益限制电阻的与连接到第二HEMT的一侧相反的一侧的开路短路，用于以预定频率和附近频率短路高频信号。

公开(公告)号：US20100156541A1

公开(公告)日：2010-06-24

申请号：US12715424

申请日：2010-03-02

Applicant: Akira Inoue ,  Seiki Goto ,  Kou Kanaya ,  Sinsuke Watanabe

Inventor： Akira Inoue ,  Seiki Goto ,  Kou Kanaya ,  Sinsuke Watanabe

IPC: H03F3/04

CPC classification number: H03F1/523 ,  H03F3/195 ,  H03F3/211 ,  H03F2200/211 ,  H03F2200/366 ,  H03F2200/381

Abstract: A current limiting circuit is connected to the gate (input terminal) of an amplifying transistor. The current limiting circuit includes a protecting transistor, a first protecting resistor connecting the drain to the gate of the protecting transistor, and a second protecting resistor connecting the source to the gate of the protecting transistor. The current limiting circuit limits current, so that electric power larger than the maximum electric power allowable for the amplifying transistor does not pass.

Abstract translation: 限流电路连接到放大晶体管的栅极（输入端）。 限流电路包括保护晶体管，将漏极连接到保护晶体管的栅极的第一保护电阻以及将源极连接到保护晶体管的栅极的第二保护电阻。 电流限制电路限制电流，使得大于放大晶体管可允许的最大电功率的功率不通过。

公开(公告)号：US07701296B2

公开(公告)日：2010-04-20

申请号：US11874966

申请日：2007-10-19

Applicant: Akira Inoue ,  Seiki Goto ,  Kou Kanaya ,  Shinsuke Watanabe

Inventor： Akira Inoue ,  Seiki Goto ,  Kou Kanaya ,  Shinsuke Watanabe

IPC: H03F3/04

CPC classification number: H03F1/523 ,  H03F3/195 ,  H03F3/211 ,  H03F2200/211 ,  H03F2200/366 ,  H03F2200/381

Abstract: A current limiting circuit is connected to the gate (input terminal) of an amplifying transistor. The current limiting circuit includes a protecting transistor, a first protecting resistor connecting the drain to the gate of the protecting transistor, and a second protecting resistor connecting the source to the gate of the protecting transistor. The current limiting circuit limits current, so that electric power larger than the maximum electric power allowable for the amplifying transistor does not pass.

Abstract translation: 限流电路连接到放大晶体管的栅极（输入端）。 限流电路包括保护晶体管，将漏极连接到保护晶体管的栅极的第一保护电阻以及将源极连接到保护晶体管的栅极的第二保护电阻。 电流限制电路限制电流，使得大于放大晶体管可允许的最大电功率的功率不通过。

公开(公告)号：US20100060362A1

公开(公告)日：2010-03-11

申请号：US12421664

申请日：2009-04-10

Applicant: Ko KANAYA ,  Seiki GOTO ,  Shinsuke WATANABE

Inventor： Ko KANAYA ,  Seiki GOTO ,  Shinsuke WATANABE

IPC: H03F3/191

CPC classification number: H03F1/226 ,  H03F1/0261 ,  H03F3/1935 ,  H03F2200/18 ,  H03F2200/27 ,  H03F2200/451 ,  H03F2200/534 ,  H03F2200/541

Abstract: A cascode circuit for a high-gain or high-output millimeter-wave device that operates with stability. The cascode circuit including two cascode-connected transistors includes: a first high electron mobility transistor (HEMT) including a source that is grounded; a second HEMT including a source connected to a drain of the first HEMT; a reflection gain restricting resistance connected to the gate of the second HEMT, for restricting reflection gain; and an open stub connected to a side of the reflection gain restricting resistance which is opposite the side connected to the second HEMT, for short-circuiting high-frequency signals at a predetermined frequency and nearby frequencies.

Abstract translation: 用于稳定运行的高增益或高输出毫米波器件的共源共栅电路。 包括两个共源共栅连接的晶体管的共源共栅电路包括：包括接地的源的第一高电子迁移率晶体管（HEMT）; 包括连接到第一HEMT的漏极的源的第二HEMT; 连接到第二HEMT的栅极的反射增益限制电阻，用于限制反射增益; 以及连接到反射增益限制电阻的与连接到第二HEMT的一侧相反的一侧的开路短路，用于以预定频率和附近频率短路高频信号。

公开(公告)号：US20080290951A1

公开(公告)日：2008-11-27

申请号：US11874966

申请日：2007-10-19

Applicant: Akira Inoue ,  Seiki Goto ,  Kou Kanaya ,  Shinsuke Watanabe

Inventor： Akira Inoue ,  Seiki Goto ,  Kou Kanaya ,  Shinsuke Watanabe

IPC: H02H7/20

CPC classification number: H03F1/523 ,  H03F3/195 ,  H03F3/211 ,  H03F2200/211 ,  H03F2200/366 ,  H03F2200/381

Abstract: A current limiting circuit is connected to the gate (input terminal) of an amplifying transistor. The current limiting circuit includes a protecting transistor, a first protecting resistor connecting the drain to the gate of the protecting transistor, and a second protecting resistor connecting the source to the gate of the protecting transistor. The current limiting circuit limits current, so that electric power larger than the maximum electric power allowable for the amplifying transistor does not pass.

Abstract translation: 限流电路连接到放大晶体管的栅极（输入端）。 限流电路包括保护晶体管，将漏极连接到保护晶体管的栅极的第一保护电阻以及将源极连接到保护晶体管的栅极的第二保护电阻。 电流限制电路限制电流，使得大于放大晶体管可允许的最大电功率的功率不通过。

公开(公告)号：US07061329B2

公开(公告)日：2006-06-13

申请号：US10792856

申请日：2004-03-05

Applicant: Akira Inoue ,  Akira Ohta ,  Seiki Goto

Inventor： Akira Inoue ,  Akira Ohta ,  Seiki Goto

IPC: H03F3/191

CPC classification number: H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6644 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H03F1/565 ,  H03F3/602 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor chip for amplification is connected between input-side and output-side matching circuits, and each of matching circuits includes balanced circuits which receive signals different in phase by 180 degrees, divided from an input signal. The balanced circuits are connected at a virtual grounding point, which is used as a grounding point sensitive to RF characteristics in an IPD. Thus, a semiconductor device can be free from influence of variations of grounding wires and can be reduced in size, weight, and cost.

Abstract translation: 用于放大的半导体芯片连接在输入侧和输出侧匹配电路之间，并且每个匹配电路包括从输入信号中分离出相位不同180度的信号的平衡电路。 平衡电路连接在虚拟接地点，用作IPD中对RF特性敏感的接地点。 因此，半导体器件可以不受接地线的变化的影响，并且可以减小尺寸，重量和成本。