WIDEBAND RECEIVER
    1.
    发明申请
    WIDEBAND RECEIVER 有权
    宽带接收机

    公开(公告)号:US20110135045A1

    公开(公告)日:2011-06-09

    申请号:US12970874

    申请日:2010-12-16

    IPC分类号: H04B1/10

    摘要: Provided is a wideband receiver that has a smaller area and consumes less power and can prevent harmonic mixing occurring due to an increase in the number of communications systems using wideband. A wideband receiver according to an aspect of the invention may include: an front-end unit receiving and performing low-pass filtering on a wideband input signal in a continuous-time domain; and a down-conversion unit sampling and holding an output signal of the front-end unit according to a local oscillator signal and performing low-pass filtering on the output signal in a discrete tie domain.

    摘要翻译: 提供了一种宽带接收机,其具有较小的面积并且消耗更少的功率,并且可以防止由于使用宽带的通信系统的数量的增加而发生谐波混合。 根据本发明的一个方面的宽带接收机可以包括:前端单元在连续时域中接收并对宽带输入信号执行低通滤波; 下变频单元根据本地振荡器信号对前端单元的输出信号进行采样和保持,并对离散的连接域中的输出信号进行低通滤波。

    DIGITAL PHASE-LOCKED LOOP WITH REDUCED LOOP DELAY
    2.
    发明申请
    DIGITAL PHASE-LOCKED LOOP WITH REDUCED LOOP DELAY 审中-公开
    数字相位锁定环路,减少环路延迟

    公开(公告)号:US20110133795A1

    公开(公告)日:2011-06-09

    申请号:US12790242

    申请日:2010-05-28

    IPC分类号: H03L7/08

    CPC分类号: H03L7/1806 H03L2207/50

    摘要: There is provided a digital phase-locked loop. A digital phase-locked loop according to an aspect of the invention may include: a reference phase accumulation unit outputting a reference sampling phase value; a phase detection unit detecting a phase difference signal; a digital loop filter filtering and averaging the phase difference signal from the phase detection unit; a digitally controlled oscillator generating an oscillation signal having a predetermined frequency; a DOC phase accumulation unit outputting the DCO sampling phase value, and generating a plurality of first to n-th D-FFs having the same frequency and different phases delayed in a sequential manner; and first to n-th D-FFs included in a closed loop including the phase detection unit, the digital loop filter, the digitally controlled oscillator, and the DOC phase accumulation unit, and operating according to the plurality of first to n-th clock signals from the DCO phase accumulation unit, respectively.

    摘要翻译: 提供了数字锁相环。 根据本发明的一个方面的数字锁相环可以包括:参考相位累积单元,输出参考采样相位值; 检测相位差信号的相位检测单元; 数字环路滤波器对来自相位检测单元的相位差信号进行滤波和平均; 产生具有预定频率的振荡信号的数字控制振荡器; DOC相位累积单元输出DCO采样相位值,并且产生具有以相继方式延迟的相同频率和不同相位的多个第一至第n个D-FF; 以及包括在相位检测单元,数字环路滤波器,数字控制振荡器和DOC相位累积单元的闭环中的第一至第N-D-FF,并且根据多个第一至第n时钟 分别来自DCO相位累积单元的信号。

    Time-to-digital converter with high resolution and wide measurement range
    3.
    发明申请
    Time-to-digital converter with high resolution and wide measurement range 有权
    具有高分辨率和宽测量范围的时间 - 数字转换器

    公开(公告)号:US20080129574A1

    公开(公告)日:2008-06-05

    申请号:US11986592

    申请日:2007-11-23

    IPC分类号: H03M1/50

    CPC分类号: G04F10/005

    摘要: A time-to-digital converter includes low and high resolution time-to-digital converters for providing both high resolution and wide measurement range. The low resolution time-to-digital converter measures a time difference between first and second signals with a first quantization step. The high resolution time-to-digital converter measures the time difference between the first and second signals with a second quantization step that is smaller than the first quantization step. The low resolution time-to-digital converter has a wider measurement range than the high resolution time-to-digital converter

    摘要翻译: 时间 - 数字转换器包括用于提供高分辨率和宽测量范围的低分辨率和高分辨率时间 - 数字转换器。 低分辨率时间 - 数字转换器利用第一量化步骤测量第一和第二信号之间的时间差。 高分辨率时间 - 数字转换器利用小于第一量化步长的第二量化步长来测量第一和第二信号之间的时间差。 低分辨率时间 - 数字转换器具有比高分辨率时间 - 数字转换器更宽的测量范围

    Time-to-digital converter with high resolution and wide measurement range
    7.
    发明授权
    Time-to-digital converter with high resolution and wide measurement range 有权
    具有高分辨率和宽测量范围的时间 - 数字转换器

    公开(公告)号:US07667633B2

    公开(公告)日:2010-02-23

    申请号:US11986592

    申请日:2007-11-23

    IPC分类号: H03M1/50

    CPC分类号: G04F10/005

    摘要: A time-to-digital converter includes low and high resolution time-to-digital converters for providing both high resolution and wide measurement range. The low resolution time-to-digital converter measures a time difference between first and second signals with a first quantization step. The high resolution time-to-digital converter measures the time difference between the first and second signals with a second quantization step that is smaller than the first quantization step. The low resolution time-to-digital converter has a wider measurement range than the high resolution time-to-digital converter.

    摘要翻译: 时间 - 数字转换器包括用于提供高分辨率和宽测量范围的低分辨率和高分辨率时间 - 数字转换器。 低分辨率时间 - 数字转换器利用第一量化步骤测量第一和第二信号之间的时间差。 高分辨率时间 - 数字转换器利用小于第一量化步长的第二量化步长来测量第一和第二信号之间的时间差。 低分辨率时间 - 数字转换器具有比高分辨率时间 - 数字转换器更宽的测量范围。

    Method of damaged low-k dielectric film layer removal
    8.
    发明申请
    Method of damaged low-k dielectric film layer removal 失效
    损坏的低k电介质膜层去除方法

    公开(公告)号:US20090173718A1

    公开(公告)日:2009-07-09

    申请号:US11644779

    申请日:2006-12-21

    IPC分类号: C23F1/00 C23F1/08

    摘要: An apparatus, system and method for removing a damaged material from a low-k dielectric film layer include identifying a control chemistry, the control chemistry configured to selectively remove the damaged material from the low-k dielectric film layer, the damaged material being in a region where a feature was formed through the low-k dielectric film layer; establishing a plurality of process parameters characterizing aspects of the damaged material to be removed and applying the control chemistry to the low-k dielectric film layer, the application of the control chemistry being defined based on the established process parameters of the damaged material, such that the damaged material is substantially removed from the areas around the feature and the areas around the feature are substantially defined by low-k characteristics of the low-k dielectric film layer.

    摘要翻译: 用于从低k电介质膜层去除损坏的材料的装置,系统和方法包括识别控制化学物质,配置为选择性地从低k电介质膜层去除损坏的材料的控制化学品,损坏的材料在 通过低k电介质膜层形成特征的区域; 建立表征要去除的损坏材料的方面的多个工艺参数,并将控制化学物质应用于低k电介质膜层,控制化学品的应用基于已建立的损坏材料的工艺参数来定义,使得 损坏的材料基本上从特征周围的区域移除,并且特征周围的区域基本上由低k电介质膜层的低k特性限定。

    High-resolution time-to-digital converter
    9.
    发明授权
    High-resolution time-to-digital converter 有权
    高分辨率时间 - 数字转换器

    公开(公告)号:US07501973B2

    公开(公告)日:2009-03-10

    申请号:US11940589

    申请日:2007-11-15

    IPC分类号: H03M1/50 H03H11/26

    CPC分类号: G04F10/005

    摘要: A time-to-digital converter includes a first delay line, a second delay line, comparators, and an encoder. The first delay line includes first resistors coupled in series and receives a first signal through a start node. The second delay line includes second resistors coupled in series and receives a second signal through a node corresponding to an end node of the first delay line. The comparators compare first voltages of nodes on the first delay line with second voltages of corresponding nodes on the second delay line. The encoder generates a digital code based on outputs of the comparators. Therefore, the time-to-digital converter may decrease a chip size thereof and lower power consumption, and the time-to-digital converter may increase a range of a maximum delay time between two signals.

    摘要翻译: 时间 - 数字转换器包括第一延迟线,第二延迟线,比较器和编码器。 第一延迟线包括串联耦合的第一电阻器,并通过起始节点接收第一信号。 第二延迟线包括串联耦合的第二电阻器,并且通过与第一延迟线的端节点对应的节点接收第二信号。 比较器将第一延迟线上的节点的第一电压与第二延迟线上的相应节点的第二电压进行比较。 编码器基于比较器的输出产生数字代码。 因此,时间 - 数字转换器可以减小其芯片尺寸并降低功耗,并且时间 - 数字转换器可以增加两个信号之间的最大延迟时间的范围。

    HIGH-RESOLUTION TIME-TO-DIGITAL CONVERTER
    10.
    发明申请
    HIGH-RESOLUTION TIME-TO-DIGITAL CONVERTER 有权
    高分辨率时间到数字转换器

    公开(公告)号:US20080136698A1

    公开(公告)日:2008-06-12

    申请号:US11940589

    申请日:2007-11-15

    IPC分类号: H03M1/00

    CPC分类号: G04F10/005

    摘要: A time-to-digital converter includes a first delay line, a second delay line, comparators, and an encoder. The first delay line includes first resistors coupled in series and receives a first signal through a start node. The second delay line includes second resistors coupled in series and receives a second signal through a node corresponding to an end node of the first delay line. The comparators compare first voltages of nodes on the first delay line with second voltages of corresponding nodes on the second delay line. The encoder generates a digital code based on outputs of the comparators. Therefore, the time-to-digital converter may decrease a chip size thereof and lower power consumption, and the time-to-digital converter may increase a range of a maximum delay time between two signals.

    摘要翻译: 时间 - 数字转换器包括第一延迟线,第二延迟线,比较器和编码器。 第一延迟线包括串联耦合的第一电阻器,并通过起始节点接收第一信号。 第二延迟线包括串联耦合的第二电阻器,并且通过与第一延迟线的端节点对应的节点接收第二信号。 比较器将第一延迟线上的节点的第一电压与第二延迟线上的相应节点的第二电压进行比较。 编码器基于比较器的输出产生数字代码。 因此,时间 - 数字转换器可以减小其芯片尺寸并降低功耗,并且时间 - 数字转换器可以增加两个信号之间的最大延迟时间的范围。